IDT 89HPES64H16G2 User Manual page 245

IDT PCI to PCI Bridge and Proprietary Port Specific Registers
Bit Field
Field Name
16 UECOMP
17 RCVOVR
18 MALFORMED
19 ECRC
20
21
PES64H16G2 User Manual
Default
Type
Value
RW 0x0
Sticky
RW 0x0
Sticky
RW 0x0
Sticky
RW 0x0
Sticky
UR RW 0x0
Sticky
ACSV RW 0x0
Sticky
Description
Unexpected Completion Mask. When this bit is set, the corre-
sponding bit in the AERUES register is masked. When a bit is
masked in the AERUES register, the corresponding event is not
logged in the advanced capability structure, the First Error Pointer
field (FEPTR) in the AERCTL register is not updated, and an error
is not reported to the root complex.
This bit does not affect the state of the corresponding bit in the
AERUES register.
Receiver Overflow Mask. When this bit is set, the corresponding
bit in the AERUES register is masked. When a bit is masked in the
AERUES register, the corresponding event is not logged in the
advanced capability structure, the First Error Pointer field (FEPTR)
in the AERCTL register is not updated, and an error is not reported
to the root complex.
This bit does not affect the state of the corresponding bit in the
AERUES register.
Malformed TLP Mask. When this bit is set, the corresponding bit
in the AERUES register is masked. When a bit is masked in the
AERUES register, the corresponding event is not logged in the
advanced capability structure, the First Error Pointer field (FEPTR)
in the AERCTL register is not updated, and an error is not reported
to the root complex.
This bit does not affect the state of the corresponding bit in the
AERUES register.
ECRC Mask. When this bit is set, the corresponding bit in the
AERUES register is masked. When a bit is masked in the AERUES
register, the corresponding event is not logged in the advanced
capability structure, the First Error Pointer field (FEPTR) in the
AERCTL register is not updated, and an error is not reported to the
root complex.
This bit does not affect the state of the corresponding bit in the
AERUES register.
UR Mask. When this bit is set, the corresponding bit in the
AERUES register is masked. When a bit is masked in the AERUES
register, the corresponding event is not logged in the advanced
capability structure, the First Error Pointer field (FEPTR) in the
AERCTL register is not updated, and an error is not reported to the
root complex.
This bit does not affect the state of the corresponding bit in the
AERUES register.
ACS Violation Mask. When this bit is set, the corresponding bit in
the AERUES register is masked. When a bit is masked in the
AERUES register, the corresponding event is not logged in the
advanced capability structure, the First Error Pointer field (FEPTR)
in the AERCTL register is not updated, and an error is not reported
to the root complex.
This bit does not affect the state of the corresponding bit in the
AERUES register.
16 - 35 April 5, 2013