IDT 89HPES64H16G2 User Manual page 244

IDT PCI to PCI Bridge and Proprietary Port Specific Registers
AERUEM - AER Uncorrectable Error Mask (0x108)
Bit
Field
0
3:1
4
5 SDOENERR
11:6
12
13
14
15
PES64H16G2 User Manual
Field Default
Type
Name Value
UDEF RW
Sticky
Reserved RO
DLPERR RW
Sticky
RW
Sticky
Reserved RO
POISONED RW
Sticky
FCPERR RW
Sticky
COMPTO RO
CABORT RO
0x0 Undefined. This bit is no longer used in this version of the specifi-
cation.
0x0 Reserved field.
0x0 Data Link Protocol Error Mask. When this bit is set, the corre-
sponding bit in the AERUES register is masked. When a bit is
masked in the AERUES register, the corresponding event is not
logged in the advanced capability structure, the First Error Pointer
field (FEPTR) in the AERCTL register is not updated, and an error
is not reported to the root complex.
This bit does not affect the state of the corresponding bit in the
AERUES register.
0x0 Surprise Down Error Mask. When this bit is set, the correspond-
ing bit in the AERUES register is masked. When a bit is masked in
the AERUES register, the corresponding event is not logged in the
advanced capability structure, the First Error Pointer field (FEPTR)
in the AERCTL register is not updated, and an error is not reported
to the root complex.
This bit does not affect the state of the corresponding bit in the
AERUES register.
0x0 Reserved field.
0x0 Poisoned TLP Mask. When this bit is set, the corresponding bit in
the AERUES register is masked. When a bit is masked in the
AERUES register, the corresponding event is not logged in the
advanced capability structure, the First Error Pointer field (FEPTR)
in the AERCTL register is not updated, and an error is not reported
to the root complex.
This bit does not affect the state of the corresponding bit in the
AERUES register.
0x0 Flow Control Protocol Error Mask. When this bit is set, the corre-
sponding bit in the AERUES register is masked. When a bit is
masked in the AERUES register, the corresponding event is not
logged in the advanced capability structure, the First Error Pointer
field (FEPTR) in the AERCTL register is not updated, and an error
is not reported to the root complex.
This bit does not affect the state of the corresponding bit in the
AERUES register.
0x0 Completion Timeout Mask. A switch port does not initiate non-
posted requests on its own behalf. Therefore, this field is hardwired
to zero.
0x0 Completer Abort Mask. The switch never responds to a non-
posted request with a completer abort, except for ACS violations.
16 - 34
Description
April 5, 2013