IDT 89HPES64H16G2 User Manual page 243

IDT PCI to PCI Bridge and Proprietary Port Specific Registers
AERUES - AER Uncorrectable Error Status (0x104)
Bit
Field
0
3:1
4
5 SDOENERR
11:6
12
13
14
15
16
17
18 MALFORMED
19
20
21
22
23
PES64H16G2 User Manual
Field Default
Type
Name Value
UDEF RW1C
Sticky
Reserved RO
DLPERR RW1C
Sticky
RW1C
Sticky
Reserved RO
POISONED RW1C
Sticky
FCPERR RW1C
Sticky
COMPTO RO
CABORT RO
UECOMP RW1C
Sticky
RCVOVR RW1C
Sticky
RW1C
Sticky
ECRC RW1C
Sticky
UR RW1C
Sticky
ACSV RW1C
Sticky
UIE RW1C
Sticky
MCBLKTLP RW1C
Sticky
0x0 Undefined. This bit is no longer used in this version of the specifi-
cation.
0x0 Reserved field.
0x0 Data Link Protocol Error Status. This bit is set when a data link
layer protocol error is detected.
0x0 Surprise Down Error Status. This bit is set when a surprise down
error is detected and the SDERR bit in the PCIELCAP register is
set.
0x0 Reserved field.
0x0 Poisoned TLP Status. This bit is set when a poisoned TLP is
detected.
0x0 Flow Control Protocol Error Status. This bit is set when a flow
control protocol error is detected.
0x0 Completion Timeout Status. A switch port does not initiate non-
posted requests on its own behalf. Therefore, this field is hardwired
to zero.
0x0 Completer Abort Status. This bit is never set as the switch never
responds to a non-posted request with a completer abort, except
for ACS violations. For this exception case, the error is an ACS vio-
lation and is not logged as a completer abort error.
0x0 Unexpected Completion Status. This bit is set when an unex-
pected completion is detected.
0x0 Receiver Overflow Status. This bit is set when a receiver over-
flow is detected.
0x0 Malformed TLP Status. This bit is set when a malformed TLP is
detected.
0x0 ECRC Status. This bit is set when an ECRC error is detected.
0x0 UR Status. This bit is set when an unsupported request is
detected.
0x0 ACS Violation Status. This bit is set when an ACS violation is
detected on the port.
0x0 Uncorrectable Internal Error Status. This bit is set when an
uncorrectable internal error associated with the port is detected.
0x0 MC Blocked TLP Status. This bit is set when a multicast TLP is
blocked by the ingress port in response to the setting of the
MC_Block_All and MC_Block_Untranslated bits in the port's multi-
cast extended capability structure.
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Description
April 5, 2013