IDT 89HPES64H16G2 User Manual page 235

IDT PCI to PCI Bridge and Proprietary Port Specific Registers
PCIELCAP2 - PCI Express Link Capabilities 2 (0x06C)
Bit
Field
31:0
PCIELCTL2 - PCI Express Link Control 2 (0x070)
Bit
Field Name
3:0
4
5
6
PES64H16G2 User Manual
Field Default
Type
Name Value
Reserved RO
Field Default
Type
Value
TLS RW
Sticky
ECOMP RW
Sticky
HASD RO
SDE RWL
0x0 Reserved field.
0x2 Target Link Speed. For downstream ports, this field sets an upper
limit on the link operational speed by restricting the values adver-
tised by the upstream component in its training sequences.
For both upstream and downstream ports, this field is used to set
the target compliance mode speed when software is using the
ECOMP bit in this register to force a link into compliance mode.
The switch supports 2.5 GT/s and 5.0 GT/s operation. Setting this
field to an unsupported value produces undefined results.
0x1 - (gen1) 2.5 GT/s
0x2 - (gen2) 5.0 GT/s
others - reserved
0x0 Enter Compliance. Software is permitted to force a link into com-
pliance mode at the speed indicated by the TLS field by setting this
bit in both components on a link and then initiating a hot reset on
the link.
0x0 Hardware Autonomous Speed Disable. When set, this bit pre-
vents hardware from changing the link speed for device specific
reasons other than to correct unreliable link operation by reducing
the link speed. Initial transition to the highest supported common
link speed is not blocked by this bit.
Switch ports do not have an autonomous mechanism to regulate
link speed, except due to link reliability issues. Therefore, this bit is
not applicable to the switch ports.
Note that this bit does not affect link speed changes triggered by
software setting the target link speed and link-retrain bits.
0x0 Selectable De-emphasis. For switch downstream ports, this bit
sets the de-emphasis level when the link operates at 5.0 GT/s. For
the upstream port, this bit selects the de-emphasis preference
advertised via training sets (the actual de-emphasis on the link is
selected by the link partner).
0x0 - De-emphasis level = -6.0 dB
0x1 - De-emphasis level = -3.5 dB
This bit has no effect when the link operates at 2.5 GT/s, or when
the link operates in low-swing mode.
When this field is modified, the newly selected de-emphasis is not
applied until the PHY LTSSM transitions through the states in
which it is allowed to modify the de-emphasis setting on the line
(e.g., Recovery.Speed). Therefore, after modifying this field, it is
recommended that the link be fully retrained by setting the FLRET
bit in the PHYLSTATE0 register.
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Description
Description
April 5, 2013