IDT 89HPES64H16G2 User Manual page 233

IDT PCI to PCI Bridge and Proprietary Port Specific Registers
PCIESSTS - PCI Express Slot Status (0x05A)
Bit
Field
0
1
2
3
4
5
6
7
PES64H16G2 User Manual
Field Default
Type
Name Value
ABP RW1C 0x0
PFD RW1C 0x0
MRLSC RW1C 0x0
PDC RW1C 0x0
CC RW1C 0x0
MRLSS RO 0x0
PDS RO 0x1
EIS RO 0x0
Description
Attention Button Pressed. Set when the attention button is
pressed.
Power Fault Detected. Set when the Power Controller detects a
power fault.
MRL Sensor Changed. Set when an MRL Sensor state change is
detected.
Presence Detected Changed. Set when a Presence Detected
change is detected.
Command Completed. This bit is set when the Hot-Plug Control-
ler completes an issued command. If the bit is already set, then it
remains set.
A single write to the PCI Express Slot Control (PCIESCTL) register
is considered to be a single command even if it affects more than
one field in that register. This command completed bit is not set
until processing of all actions associated with all fields in the PCI-
ESCTL register have completed (i.e., all associated SMBus I/O
expander transactions have completed).
MRL Sensor State. This field enclosed the current state of the
MRL sensor.
0x0 - (closed) MRL closed
0x1 - (open) MRL open
Presence Detect State. When the Slot Implemented (SLOT) bit is
set in the PCI Express Capabilities (PCIECAP) register, this bit
indicates the presence of a card in the slot corresponding to the
port and reflects the state of the Presence Detect status.
When the SLOT bit is cleared in the PCIECAP register, this bit is
hardwired to one in downstream ports (i.e., it is read-only with a
constant value of one).
This bit is always cleared in upstream ports (i.e., it is read-only with
a constant value of zero).
0x0 - (empty) Slot empty
0x1 - (present) Card present
Electromechanical Interlock Status. When an electromechanical
interlock is implemented, this bit indicates the current status of the
interlock.
The status of this bit is determined by the state of the correspond-
ing PxILOCKST input signal on I/O expander 9. If the hot-plug sig-
nals associated with the port are mapped to GPIO pins or if I/O
expander is not enabled, then the state of this bit defaults to zero
(i.e., disengaged).
0x0 - (disengaged) Electromechanical interlock disengaged
0x1 - (engaged) Electromechanical interlock engaged
16 - 23 April 5, 2013