IDT 89HPES64H16G2 User Manual page 232

IDT PCI to PCI Bridge and Proprietary Port Specific Registers
Bit Field
Field Name
7:6
9:8
10
11
12 DLLLASCE
15:13 Reserved
PES64H16G2 User Manual
Default
Type
Value
AIC RW HWINIT
PIC RW HWINIT
PCC RW HWINIT
EIC RW HWINIT
RW HWINIT
RO 0x0
Description
Attention Indicator Control. When read, this register returns the
current state of the Attention Indicator. Writing to this register sets
the indicator.
This bit is read-only and has a value of zero when the correspond-
ing capability is not enabled in the PCIESCAP register.
This field is always zero if the ATTIP bit is cleared in the PCIES-
CAP register.
When the corresponding capability is enabled, the initial value of
this field is equal to the value of the corresponding field in the PCI-
ESCTLIV register.
0x0 - (reserved) Reserved
0x1 (on) On
0x2 - (blink) Blink
0x3 - (off) Off
Power Indicator Control. When read, this register returns the cur-
rent state of the Power Indicator. Writing to this register sets the
indicator.
This bit is read-only and has a value of zero when the correspond-
ing capability is not enabled in the PCIESCAP register.
This field is always zero if the PWRIP bit is cleared in the PCIES-
CAP register.
When the corresponding capability is enabled, the initial value of
this field is equal to the value of the corresponding field in the PCI-
ESCTLIV register.
0x0 - (reserved) Reserved
0x1 - (on) On
0x2 - (blink) Blink
0x3 - (off) Off
This field has no effect on the upstream port.
Power Controller Control. When read, this register returns the
current state of the power applied to the slot. Writing to this register
sets the power state of the slot.
This bit is read-only and has a value of zero when the correspond-
ing capability is not enabled in the PCIESCAP register.
When the corresponding capability is enabled, the initial value of
this field is equal to the value of the corresponding field in the PCI-
ESCTLIV register.
0x0 -(on) Power on
0x1 -(off) Power off
Electromechanical Interlock Control. This field always returns a
value of zero when read. If an electromechanical interlock is imple-
mented, a write of a one to this field causes the state of the inter-
lock to toggle and a write of a zero has no effect.
This bit is read-only and has a value of zero when the correspond-
ing capability is not enabled in the PCIESCAP register.
Data Link Layer Link Active State Change Enable. This bit
when set enables generation of a Hot-Plug interrupt or wake-up
event on a data link layer active field state change.
When the corresponding capability is enabled, the initial value of
this field is equal to the value of the corresponding field in the PCI-
ESCTLIV register.
Reserved field.
16 - 22 April 5, 2013