IDT 89HPES64H16G2 User Manual page 231

IDT PCI to PCI Bridge and Proprietary Port Specific Registers
PCIESCTL - PCI Express Slot Control (0x058)
Bit
Field
0
1
2
3
4
5
PES64H16G2 User Manual
Field Default
Type
Name Value
ABPE RW HWINIT
PFDE RW HWINIT
MRLSCE RW HWINIT
PDCE RW HWINIT
CCIE RW HWINIT
HPIE RW HWINIT
Description
Attention Button Pressed Enable. This bit when set enables
generation of a Hot-Plug interrupt or wake-up event on an attention
button pressed event.
This bit is read-only and has a value of zero when the correspond-
ing capability is not enabled in the PCIESCAP register.
When the corresponding capability is enabled, the initial value of
this field is equal to the value of the corresponding field in the PCI-
ESCTLIV register.
Power Fault Detected Enable. This bit when set enables the gen-
eration of a Hot-Plug interrupt or wake-up event on a power fault
event.
This bit is read-only and has a value of zero when the correspond-
ing capability is not enabled in the PCIESCAP register.
When the corresponding capability is enabled, the initial value of
this field is equal to the value of the corresponding field in the PCI-
ESCTLIV register.
MRL Sensor Change Enable. This bit when set enables the gen-
eration of a Hot-Plug interrupt or wake-up event on a MRL sensor
change event.
This bit is read-only and has a value of zero when the correspond-
ing capability is not enabled in the PCIESCAP register.
When the corresponding capability is enabled, the initial value of
this field is equal to the value of the corresponding field in the PCI-
ESCTLIV register.
Presence Detected Changed Enable. This bit when set enables
the generation of a Hot-Plug interrupt or wake-up event on a pres-
ence detect change event.
This bit is read-only and has a value of zero when the correspond-
ing capability is not enabled in the PCIESCAP register.
When the corresponding capability is enabled, the initial value of
this field is equal to the value of the corresponding field in the PCI-
ESCTLIV register.
Command Complete Interrupt Enable. This bit when set enables
the generation of a Hot-Plug interrupt when a command is com-
pleted by the Hot-Plug Controller.
This bit is read-only and has a value of zero when the correspond-
ing capability is not enabled in the PCIESCAP register.
When the corresponding capability is enabled, the initial value of
this field is equal to the value of the corresponding field in the PCI-
ESCTLIV register.
Hot Plug Interrupt Enable. This bit when set enables generation
of a Hot-Plug interrupt on enabled Hot-Plug events.
This bit is read-only and has a value of zero when the correspond-
ing capability is not enabled in the PCIESCAP register.
When the corresponding capability is enabled, the initial value of
this field is equal to the value of the corresponding field in the PCI-
ESCTLIV register.
16 - 21 April 5, 2013