IDT 89HPES64H16G2 User Manual page 230

IDT PCI to PCI Bridge and Proprietary Port Specific Registers
Bit Field
Field Name
5
6
14:7
16:15
17
18 NCCS
31:19 PSLOTNUM
PES64H16G2 User Manual
Default
Type
Value
HPS RWL 0x0
HPC RWL 0x0
SPLV RW 0x0
SPLS RW 0x0
EIP RWL 0x0
RO 0x0
RWL 0x0
Description
Hot Plug Surprise. When set, this bit indicates that a device pres-
ent in the slot may be removed from the system without notice.
This bit is read-only and has a value of zero when the SLOT bit in
the PCIECAP register is cleared.
Hot Plug Capable. This bit is set if the slot corresponding to the
port is capable of supporting hot-plug operations.
This bit is read-only and has a value of zero when the SLOT bit in
the PCIECAP register is cleared.
Slot Power Limit Value. In combination with the Slot Power Limit
Scale, this field specifies the upper limit on power supplied by the
slot.
A Set_Slot_Power_Limit message is generated using this field
whenever this register is written or when the link transitions from a
non DL_Up status to a DL_Up status.
This bit is read-only and has a value of zero when the SLOT bit in
the PCIECAP register is cleared.
Slot Power Limit Scale. This field specifies the scale used for the
Slot Power Limit Value (SPLV).
0x0 - (x1) 1.0x
0x1 - (xp1) 0.1x
0x2 - (xp01) 0.01x
0x3 - (xp001) 0.001x
A Set_Slot_Power_Limit message is generated using this field
whenever this register is written or when the link transitions from a
non DL_Up status to a DL_Up status.
This bit is read-only and has a value of zero when the SLOT bit in
the PCIECAP register is cleared.
Electromechanical Interlock Present. This bit is set if an electro-
mechanical interlock is implemented on the chassis for this slot.
This bit is read-only and has a value of zero when the SLOT bit in
the PCIECAP register is cleared.
No Command Completed Support. Software notification is
always generated when an issued command is completed by the
hot-plug controller. Therefore, this field is hardwired to zero.
Physical Slot Number. This field indicates the physical slot num-
ber attached to this port. For devices interconnected on the system
board, this field should be initialized to zero.
This bit is read-only and has a value of zero when the SLOT bit in
the PCIECAP register is cleared.
16 - 20 April 5, 2013