IDT 89HPES64H16G2 User Manual page 229

IDT PCI to PCI Bridge and Proprietary Port Specific Registers
Bit
Field
14
15
PCIESCAP - PCI Express Slot Capabilities (0x054)
Bit
Field
0
1
2
3
4
PES64H16G2 User Manual
Field Default
Type
Name Value
LBWSTS RW1C 0x0
LABWSTS RW1C 0x0
Field Default
Type
Name Value
ABP RWL 0x0
PCP RWL 0x0
MRLP RWL 0x0
ATTIP RWL 0x0
PWRIP RWL 0x0
Description
Link Bandwidth Management Status. This bit is set to indicate
that either of the following have occurred without the link transition-
ing through the DL_Down state.
A link retraining initiated by setting the LRET bit in the PCIELCTL
register has completed.
The PHY has autonomously changed link speed or width to
attempt to correct unreliable link operation either through an
LTSSM time-out or a higher level process.
This bit must be set if the Physical Layer reports a speed or width
change was initiated by the downstream component that was not
indicated as an autonomous change.
If the LBN field in the PCIELCAP register is cleared, this field is
hardwired to zero.
This field is hardwired to zero in an upstream port.
Link Autonomous Bandwidth Status. This bit is set to indicate
that either that the PHY has autonomously changed link speed or
width for reasons other than to attempt to correct unreliable link
operation.
This bit must be set if the Physical Layer reports a speed or width
change was initiated by the downstream component that was indi-
cated as an autonomous change.
If the LBN field in the PCIELCAP register is cleared, this field is
hardwired to zero.
This field is hardwired to zero in an upstream port.
Description
Attention Button Present. This bit is set when the Attention But-
ton is implemented for the port.
This bit is read-only and has a value of zero when the SLOT bit in
the PCIECAP register is cleared.
Power Control Present. This bit is set when a Power Controller is
implemented for the port.
This bit is read-only and has a value of zero when the SLOT bit in
the PCIECAP register is cleared.
MRL Sensor Present. This bit is set when an MRL Sensor is
implemented for the port.
This bit is read-only and has a value of zero when the SLOT bit in
the PCIECAP register is cleared.
Attention Indicator Present. This bit is set when an Attention
Indicator is implemented for the port.
This bit is read-only and has a value of zero when the SLOT bit in
the PCIECAP register is cleared.
Power Indicator Present. This bit is set when an Power Indicator
is implemented for the port.
This bit is read-only and has a value of zero when the SLOT bit in
the PCIECAP register is cleared.
16 - 19 April 5, 2013