IDT 89HPES64H16G2 User Manual page 228

IDT PCI to PCI Bridge and Proprietary Port Specific Registers
PCIELSTS - PCI Express Link Status (0x052)
Bit
Field
3:0
9:4
10
11
12
13
PES64H16G2 User Manual
Field Default
Type
Name Value
CLS RO 0x1
NLW RO HWINIT
Reserved RO 0x0
LTRAIN RO 0x0
SCLK RWL HWINIT
DLLLA RO 0x0
Description
Current Link Speed. This field indicates the current link speed of
the port.
1 - (gen1) 2.5 GT/s
2 - (gen2) 5 GT/s
others - reserved
Negotiated Link Width. This field indicates the negotiated width of
the link.
00 0001b - x1
00 0010b - x2
00 0100b - x4
00 1000b - x8
00 1100b - x12
01 0000b - x16
10 0000b - x32
When the MAXLNKWDTH field in the PCIELCAP register selects a
width not supported by the port, the value of this field corresponds
to the setting of the MAXLNKWDTH field, regardless of the actual
negotiated link width.
When the MAXLNKWDTH field in the PCIELCAP register selects a
width supported by the port, but the link is unable to train, the value
in this field is set to 0x0.
Reserved field.
Link Training. When set, this bit indicates that link training is in
progress.
This bit is set when the Physical Layer LTSSM is in Configuration
or Recovery State, or when 0x1 is written to LRET bit in the
PCIELCTL register but Link training has not yet begun.
Hardware clears this bit when LTSSM exits Configuration/ Recov-
ery State.
This bit is only valid when the port operates in 'Downstream Switch
Port' mode. Else, this bit always has a value of 0x0.
Slot Clock Configuration. When set, this bit indicates that the
port uses the same physical reference clock used by its link partner
(i.e., common-clock configuration). The initial value of this field
depends on the port's clocking mode. Refer to Table 4.1 for further
details.
Data Link Layer Link Active. This bit indicates the status for the
data link control and management state machine.
0x0 - (not_active) Data link layer not active state
0x1 - (active) Data link layer active state
This bit must never be set by hardware if the DLLLA bit in the
PCIELCAP register is cleared.
16 - 18 April 5, 2013