IDT 89HPES64H16G2 User Manual page 227

IDT PCI to PCI Bridge and Proprietary Port Specific Registers
Bit Field
Field Name
5 LRET
6 CCLK
7 ESYNC
8 CLKPWRMGT
9 HAWD
10 LBWINTEN
11 LABWINTEN
15:12 Reserved
PES64H16G2 User Manual
Default
Type
Value
Upstream 0x0 Link Retrain. Writing a one to this field initiates Link retraining by
Port: directing the Physical Layer LTSSM to the Recovery state. This
RWL field always returns zero when read.
It is permitted to set this bit while simultaneously modifying other
Down- fields in this register.
stream When this bit is set and the LTSSM is already in the Recovery or
Port: Configuration states, all modifications that affect link retraining are
RW applied in the subsequent retraining. Else, if the LTSSM is not in
the Recovery or Configuration states, modifications that affect link
retraining are applied immediately.
RW 0x0 Common Clock Configuration. When set, this bit indicates that
this port and the port at the opposite end of the link are operating
with a distributed common reference clock.
After modifying this bit in both components of the link, software
must trigger a link retrain by setting the link retrain bit in the
upstream component's Link Control register.
In the switch, the L0s and L1 exit latencies do not change among
common and non-common clock configurations.
RW 0x0 Extended Syncb When set this bit forces transmission of addi-
tional ordered sets when exiting the L0s state and when in the
recovery state.
RO 0x0 Enable Clock Power Management. The switch does not support
this feature.
RO 0x0 Hardware Autonomous Width Disable. When set, this bit dis-
ables hardware from changing the link width for reasons other than
attempting to correct for unreliable link operation by reducing the
link width.
The switch ports do not have a hardware autonomous mechanism
to change link width, except due to link reliability issues. Therefore,
this bit is not applicable and is hardwired to zero.
Note that this bit does not affect link width changes triggered by the
link width re-configuration mechanism.
RW 0x0 Link Bandwidth Management Interrupt Enable. When set, this
bit enables the generation of an interrupt to indicate that the
LBWSTS bit has been set in the PCIELSTS register.
If the LBN field in the PCIELCAP register is cleared, this field is
hardwired to zero.
This field is hardwired to zero in an upstream port.
RW 0x0 Link Autonomous Bandwidth Interrupt Enable. When set, this
bit enables the generation of an interrupt to indicate that the
LABWSTS bit has been set in the PCIELSTS register.
If the LBN field in the PCIELCAP register is cleared, this field is
hardwired to zero.
This field is hardwired to zero in an upstream port.
RO 0x0 Reserved field.
16 - 17
Description
April 5, 2013