IDT PCI to PCI Bridge and Proprietary Port Specific Registers
Bit
Field
Name
21
23:22
Reserved
31:24
PORTNUM
PCIELCTL - PCI Express Link Control (0x050)
Bit
Field
1:0
2
Reserved
3
4
PES64H16G2 User Manual
Field
Default
Type
Value
LBN
RWL
Upstream:
Downstream:
RO
RO
Port 0: 0x0
Port 1: 0x1
Port 2: 0x2
Port 3: 0x3
Port 4: 0x4
Port 5: 0x5
Port 6: 0x6
Port 7: 0x7
Port 8: 0x8
Port 9: 0x9
Port 10: 0xA
Port 11: 0xB
Port 12: 0xC
Port 13: 0xD
Port 14: 0xE
Port 15: 0xF
Field
Default
Type
Name
Value
ASPM
RW
RO
RCB
RO
LDIS
RW
Link Bandwidth Notification Capability. When set, this bit indi-
0x0
cates support for the link bandwidth notification status and interrupt
mechanisms. The switch downstream ports support the capability.
This field is not applicable for the upstream port and must be zero.
0x1
0x0
Reserved field.
Port Number. This field indicates the PCI express port number for
the corresponding link.
0x0
Active State Power Management (ASPM) Control. This field
controls the level of ASPM supported by the link. The initial value
corresponds to disabled. The value contained in Serial EEPROM
may override this default value
0x0 - (disabled) disabled
0x1 - (l0s) L0s enable entry
0x2 - (l1) L1 enable entry
0x3 - (l0sl1) L0s and L1 enable entry
Note that "L0s enable entry" corresponds to the transmitter enter-
ing L0s (the receiver supports this function and is not affected by
this setting).
0x0
Reserved field.
0x0
Read Completion Boundary. This field is not applicable and is
hardwired to zero.
0x0
Link Disable. When set in a downstream port, this bit disables the
link. This bit is not applicable on an upstream port.
16 - 16
Description
Description
April 5, 2013
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