IDT 89HPES64H16G2 User Manual page 225

IDT PCI to PCI Bridge and Proprietary Port Specific Registers
Bit Field
Field Name
9:4 MAXLNK-
WDTH
11:10 ASPMS
14:12 L0SEL
17:15 L1EL
18 CPM
19 SDERR
20 DLLLA
PES64H16G2 User Manual
Default
Type
Value
RWL HWINIT Maximum Link Width. This field indicates the maximum link width
of the given PCI Express link. This field may be overridden to allow
the link width to be forced to a smaller value.
Setting this field to an invalid or reserved value is allowed and
results in the port operating at its default (i.e., initial) value. The
value written to this field is never modified by hardware
0 - reserved
1 - (x1) x1 link width
2 - (x2) x2 link width
4 - (x4) x4 link width
8 - (x8) x8 link width
12 - (x12) x12 link width
16 - (x16) x16 link width
32 - (x32) x32 link width
others - reserved
Note: This field must only be modified when reducing to reduce the
port's maximum link width default value. Otherwise, operation is
undefined.
In addition, modifying this field when the port is in an operating
mode other than disabled causes the port to immediately re-train
the link via the PHY's Recovery and Configuration states. This
immediate transition may result in receiver errors being logged in
the AER Correctable Error Status (AERCES) register.
RWL 0x3 Active State Power Management (ASPM) Support. This default
value of this field is 0x3 to indicate that L0s and L1 are supported.
This field may be overridden to allow user control over the ASPM
capabilities of this port (L0s and/or L1).
RWL 0x6 L0s Exit Latency. This field indicates the L0s exit latency for the
given PCI Express link. Transitioning from L0s to L0 always
requires approximately 2.04µs. Thus, default value indicates an
L0s exit latency between 2µs and 4µs.
RWL 0x2 L1 Exit Latency. This field indicates the L1 exit latency for the
given PCI Express link. Transitioning from L1 to L0 always requires
approximately 2.3µs. Therefore, a value 2µs to less than 4 µs is
reported with a default value of 0x2.
RWL 0x0 Clock Power Management. This bit indicates if the component
tolerates removal of the reference clock via the "CLKREQ#" mach-
anism.
The switch does not support the removal of reference clocks.
RWL Upstream: Surprise Down Error Reporting. The switch dDownstream ports
0x0 support surprise down error reporting.
This field does not apply to an upstream port and should be hard-
Downstream: wired to zero.
0x1
RWL Upstream: Data Link Layer Link Active Reporting. The switch downstream
0x0 ports support the capability of reporting the DL_Active state of the
data link control and management state machine.
Downstream: This field is not applicable for the upstream port and must be hard-
0x1 wired to zero.
16 - 15
Description
April 5, 2013