IDT 89HPES64H16G2 User Manual page 220

IDT PCI to PCI Bridge and Proprietary Port Specific Registers
BCTL - Bridge Control Register (0x03E)
Bit
Field
0
1
2
3
4
5
6
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PES64H16G2 User Manual
Field Default
Type
Name Value
PERRE RW 0x0
SERRE RW 0x0
ISAEN RW 0x0
VGAEN RW 0x0
VGA16EN RW 0x0
Reserved RO 0x0
SRESET RW 0x0
Reserved RO 0x0
Description
Parity Error Response Enable. This bit controls the logging of
poisoned TLPs in the Master Data Parity Error bit (MDPED) in the
Secondary Status (SECSTS) register.
System Error Enable. This bit controls forwarding of ERR_COR,
ERR_NONFATAL, ERR_FATAL from the secondary interface of
the bridge to the primary interface.
Note that error reporting must be enabled in the Command register
or PCI Express Capability structure, Device Control register for
errors to be reported on the primary interface.
0x0 -(ignore) Do not forward errors from the secondary to the pri-
mary interface.
0x1 - (report) Enable forwarding of errors from secondary to the
primary interface.
ISA Enable. This bit controls the routing of ISA I/O transactions.
0 - (disable) Forward downstream all I/O addresses in the address
range defined by the I/O base and I/O limit registers
1 - (enable) Forward upstream ISA I/O addresses in the address
range defined by the I/O base and I/O limit registers that are in
the first 64 KB of PCI I/O address space (top 768 bytes of each
1-KB block)
VGA Enable. Controls the routing of processor-initiated transac-
tions targeting VGA.
0 - (block) Do not forward VGA compatible addresses from the pri-
mary interface to the secondary interface
1 - (forward) Forward VGA compatible addresses from the primary
to the secondary interface.
VGA 16-bit Enable. This bit only has an effect when the VGAEN
bit is set in this register.
This read/write bit enables system configuration software to select
between 10-bit and 16-bit I/O space decoding for VGA transac-
tions.
0 - (bit10) Perform 10-bit decoding. I/O space aliasing occurs in
this mode.
1 - (bit16) Perform 16-bit decoding. No I/O space aliasing occurs in
this mode.
Reserved field.
Secondary Bus Reset. Setting this bit triggers a secondary bus
reset.
In the upstream port, setting this bit initiates a Upstream Second-
ary Bus Reset.
In a downstream port, setting this bit initiates a Downstream Sec-
ondary Bus Reset.
Port Configuration Registers must not be changed except as
required to update port status.
Reserved field.
16 - 10 April 5, 2013