IDT 89HPES64H16G2 User Manual page 219

IDT PCI to PCI Bridge and Proprietary Port Specific Registers
CAPPTR - Capabilities Pointer Register (0x034)
Bit
Field
7:0
EROMBASE - Expansion ROM Base Address Register (0x038)
Bit
Field
31:0 EROMBASE
INTRLINE - Interrupt Line Register (0x03C)
Bit
Field
7:0
INTRPIN - Interrupt PIN Register (0x03D)
Bit
Field
7:0
PES64H16G2 User Manual
Field Default
Type
Name Value
CAPPTR RWL 0x40
Field Default
Type
Name Value
RO 0x0
Field Default
Type
Name Value
INTRLINE RW 0x0
Field Default
Type
Name Value
INTRPIN RWL 0x0
Description
Capabilities Pointer. This field specifies a pointer to the head of
the capabilities structure.
Description
Expansion ROM Base Address. The bridge does not implement
an expansion ROM. Thus, this field is hardwired to zero.
Description
Interrupt Line. This register communicates interrupt line routing
information. Values in this register are programmed by system
software and are system architecture specific. The bridge does not
use the value in this register. Legacy interrupts may be imple-
mented by downstream ports.
Description
Interrupt Pin. Interrupt pin or legacy interrupt messages are not
used by the internal P2P bridges by default. However, they can be
used for hot-plug by the downstream ports.
This field should only be configured with values of 0x0 through 0x4.
The switch's bridges may only be configured to generate INTA
interrupts. Therefore, correct values for this field are only 0x0 and
0x1.
0x0 - (none) Bridge does not generate any interrupts.
0x1 - (INTA) Bridge generates INTA interrupts.
0x2 - (INTB) Bridge generates INTB interrupts.
0x3 - (INTC) Bridge generates INTC interrupts.
0x4 - (INTD) Bridge generates INTD interrupts.
16 - 9 April 5, 2013