IDT 89HPES64H16G2 User Manual page 218

IDT PCI to PCI Bridge and Proprietary Port Specific Registers
Bit
Field
3:1
15:4
PMBASEU - Prefetchable Memory Base Upper Register (0x028)
Bit
Field
31:0 PMBASEU
PMLIMITU - Prefetchable Memory Limit Upper Register (0x02C)
Bit
Field
31:0
IOBASEU - I/O Base Upper Register (0x030)
Bit
Field
15:0
IOLIMITU - I/O Limit Upper Register (0x032)
Bit
Field
15:0
PES64H16G2 User Manual
Field Default
Type
Name Value
Reserved RO 0x0
PMLIMIT RW 0x0
Field Default
Type
Name Value
RW 0xFFFF_FFFF
Field Default
Type
Name Value
PMLIMITU RW 0x0
Field Default
Type
Name Value
IOBASEU RW 0xFFFF
Field Default
Type
Name Value
IOLIMITU RW 0x0
Description
Reserved field.
Prefetchable Memory Address Limit. The PMBASE, PMBASEU,
PMLIMIT and PMLIMITU registers are used to control the forward-
ing of prefetchable transactions between the primary and second-
ary interfaces of the bridge. This field contains A[31:20] of the
highest memory address, with A[19:0] assumed to be 0xF_FFFF,
that is below the primary interface of the bridge. PMLIMITU speci-
fies the remaining bits
Description
Prefetchable Memory Address Base Upper. This field specifies
the upper 32-bits of PMBASE when 64-bit addressing is used.
When the PMCAP field in the PMBASE register is cleared, this
field becomes read-only with a value of zero.
Description
Prefetchable Memory Address Limit Upper. This field specifies
the upper 32-bits of PMLIMIT.
When the PMCAP field in the PMBASE register is cleared, this
field becomes read-only with a value of zero.
Description
I/O Address Base Upper. This field specifies the upper 16-bits of
IOBASE.
When the IOCAP field in the IOBASE register is cleared, this field
becomes read-only with a value of zero.
Description
IO Limit Upper. This field specifies the upper 16-bits of IOLIMIT.
When the IOCAP field in the IOBASE register is cleared, this field
becomes read-only with a value of zero.
16 - 8 April 5, 2013