IDT 89HPES64H16G2 User Manual page 216

IDT PCI to PCI Bridge and Proprietary Port Specific Registers
IOLIMIT - I/O Limit Register (0x01D)
Bit
Field
0
3:1
7:4
SECSTS - Secondary Status Register (0x01E)
Bit
Field
7:0
8
10:9
11
12
13
14
15
PES64H16G2 User Manual
Field Default
Type
Name Value
IOCAP RO 0x1
Reserved RO 0x0
IOLIMIT RW 0x0
Field Default
Type
Name Value
Reserved RO 0x0
MDPED RW1C 0x0
DVSEL RO 0x0
STAS RW1C 0x0
RTAS RO 0x0
RMAS RO 0x0
RSE RW1C 0x0
DPE RW1C 0x0
Description
I/O Capability. Indicates if the bridge supports 16-bit or 32-bit I/O
addressing. This bit always reflects the value of the IOCAP field in
the IOBASE register.
Reserved field.
I/O Limit. The IOBASE and IOLIMIT registers are used to control
the forwarding of I/O transactions between the primary and sec-
ondary interfaces of the bridge. This field contains A[15:12] of the
highest I/O address, with A[11:0] assumed to be 0xFFF, that is
below the primary interface of the bridge.
Description
Reserved field.
Master Data Parity Error. This bit is set by the bridge function if
the PERRE bit in the Bridge Control (BCTL) register is set to 0x1
and either of the following two conditions occurs: the function
receives a Poisoned Completion going Upstream, or the function
transmits a Poisoned Request Downstream.
Not applicable.
Signaled Target Abort Status. This bit is set when the bridge
completes a posted or non-posted request with a completer-abort
error on its secondary side. In the switch, this bit is set when the
bridge completes a posted or non-posted request received on its
secondary side with completer-abort status as a result of an ACS
violation, or when the bridge blocks a multicast TLP received on its
secondary side.
Received Target Abort Status. Not applicable (the internal P2P
bridges within the switch never generate requests on their own
behalf).
Received Master Abort Status. Not applicable ((the internal P2P
bridges within the switch never generate requests on their own
behalf).
Received System Error. This bit is set if the secondary side of the
bridge receives an ERR_FATAL or ERR_NONFATAL message.
Detected Parity Error. This bit is set by the internal bridges within
the switch whenever they receive a poisoned TLP on the second-
ary side regardless of the state of the PERRE bit in the PCI Com-
mand register.
16 - 6 April 5, 2013