IDT 89HPES64H16G2 User Manual page 19

Notes
PES64H16G2 User Manual
®
Figure 1.1 PES64H16G2 Block Diagram ............................................................................................1-4
Figure 1.2 PES64H16G2 Logic Diagram ............................................................................................1-5
Figure 2.1 PES64H16G2 Block Diagram ............................................................................................2-1
Figure 2.2 Transparent PCIe Switch ...................................................................................................2-2
Figure 2.3 Partitionable PCI Express Switch ......................................................................................2-2
Figure 3.1 Crossbar Connection to Port Ingress and Egress Buffers .................................................3-3
Figure 3.2 Architectural Model of Arbitration .......................................................................................3-6
Figure 3.3 PCIe Switch Static Rate Mismatch ....................................................................................3-9
Figure 3.4 PCIe Switch Static Rate Mismatch ....................................................................................3-9
Figure 3.5 Request Metering Count and Initial Value Loaded ..........................................................3-10
Figure 3.6 Decrement Value and Decrement Value Adjustment .......................................................3-11
Figure 3.7 Request Metering Counter Decrement Operation ............................................................3-12
Figure 3.8 Non-Posted Read Request Completion Size Estimate Computation ...............................3-12
Figure 4.1 Logical Representation of the PES64H16G2 Clocking Architecture ..................................4-1
Figure 5.1 Switch Fundamental Reset with Serial EEPROM Initialization ..........................................5-5
Figure 5.2 Fundamental Reset Using RSTHALT to Keep Device in Quasi-Reset State .....................5-5
Figure 6.1 Allowable Partition State Transitions .................................................................................6-2
Figure 7.1 Unmerged Port Lane Reversal for Maximum Link Width of x4 ..........................................7-2
Figure 7.2 Unmerged Port Lane Reversal for Maximum Link Width of x2 ..........................................7-2
Figure 7.3 Merged Port Lane Reversal for Maximum Link Width of x2) ..............................................7-3
Figure 7.4 Merged Port Lane Reversal for Maximum Link Width of x4 ...............................................7-4
Figure 7.5 Merged Port Lane Reversal for Maximum Link Width of x8 ...............................................7-5
Figure 7.6 PES64H16G2 ASPM Link Sate Transitions .....................................................................7-11
Figure 8.1 De-emphasis Applied on Link as a Function of the Fine de-emphasis and Transmit
Drive Level Controls, when the PHY Operates in Gen1 Data Rate with -3.5 dB
Nominal de-emphasis ......................................................................................................8-10
Figure 8.2 De-emphasis Applied on Link as a Function of the Fine de-emphasis and Transmit
Drive Level Controls, when the PHY Operates in Gen2 Data Rate with -3.5 dB
Nominal de-emphasis ......................................................................................................8-10
Figure 8.3 De-emphasis Applied on Link as a Function of the Fine de-emphasis and Transmit
Drive Level Controls, when the PHY Operates in Gen1 Data Rate with -6.0 dB
Nominal de-emphasis ......................................................................................................8-11
Figure 9.1 ACS Source Validation Example .......................................................................................9-4
Figure 9.2 ACS Peer-to-Peer Request Re-direct at a Downstream Port ............................................9-4
Figure 9.3 ACS Upstream Forwarding Example .................................................................................9-5
Figure 9.4 Error Checking and Logging on a Received TLP .............................................................9-15
Figure 10.1 Hot-Plug on Switch Downstream Slots Application ..........................................................10-1
Figure 10.2 Hot-Plug with Switch on Add-In Card Application ............................................................10-2
Figure 10.3 Hot-Plug with Carrier Card Application ............................................................................10-2
Figure 10.4 Power Enable Controlled Reset Output Mode Operation ................................................10-5
Figure 10.5 Power Good Controlled Reset Output Mode Operation ...................................................10-6
Figure 10.6 PES64H16G2 Hot-Plug Event Signalling .........................................................................10-8
Figure 11.1 PES64H16G2 Power Management State Transition Diagram .........................................11-2
Figure 13.1 Split SMBus Interface Configuration ................................................................................13-1
Figure 13.2 Single Double Word Initialization Sequence Format ........................................................13-3
Figure 13.3 Sequential Double Word Initialization Sequence Format .................................................13-4
Figure 13.4 Configuration Done Sequence Format ............................................................................13-4
Figure 13.5 Slave SMBus Command Code Format ..........................................................................13-15
Figure 13.6 CSR Register Read or Write CMD Field Format ............................................................13-16
List of Figures
ix April 5, 2013