IDT 89HPES64H16G2 User Manual page 18

Pci express
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IDT List of Tables
Notes
PES64H16G2 User Manual
Table 12.2
General Purpose I/O Pin Alternate Function ..................................................................... 12-2
Table 12.3
GPIO Alternate Function Pins ........................................................................................... 12-3
Serial EEPROM SMBus Address ...................................................................................... 13-2
PES64H16G2 Compatible Serial EEPROMs .................................................................... 13-2
Serial EEPROM Initialization Errors .................................................................................. 13-5
I/O Expander Function Allocation ...................................................................................... 13-6
I/O Expander Default Output Signal Value ........................................................................ 13-7
Table 13.6
Pin Mapping for I/O Expanders 0 through 7 ...................................................................... 13-9
Pin Mapping I/O Expander 8 ........................................................................................... 13-10
Table 13.8
Pin Mapping I/O Expander 9 ........................................................................................... 13-11
Table 13.9
Pin Mapping I/O Expander 10 ......................................................................................... 13-12
Table 13.10 I/O Expander 11 - Partition Fundamental Reset Inputs................................................... 13-12
Table 13.11 I/O Expander 12 - Link Up Status.................................................................................... 13-13
Table 13.12 I/O Expander 13 - Link Activity Status ............................................................................. 13-14
Table 13.13 Slave SMBus Address..................................................................................................... 13-14
Table 13.14 Slave SMBus Command Code Fields ............................................................................. 13-15
Table 13.15 CSR Register Read or Write Operation Byte Sequence ................................................. 13-16
Table 13.16 CSR Register Read or Write CMD Field Description....................................................... 13-17
Table 13.17 Serial EEPROM Read or Write Operation Byte Sequence ............................................. 13-17
Table 13.18 Serial EEPROM Read or Write CMD Field Description................................................... 13-18
Global Address Space Organization ................................................................................. 15-1
Default PCI Capability List Linkage ................................................................................... 15-4
Default PCI Express Capability List Linkage ..................................................................... 15-4
PCI-to-PCI Bridge Configuration Space Registers ............................................................ 15-6
Proprietary Port Specific Registers.................................................................................. 15-11
Switch Configuration and Status ..................................................................................... 15-13
JTAG Pin Descriptions ...................................................................................................... 18-2
Boundary Scan Chain........................................................................................................ 18-3
Instructions Supported by the JTAG Boundary Scan ........................................................ 18-8
System Controller Device Identification Register .............................................................. 18-9
viii
April 5, 2013

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