IDT 89HPES64H16G2 User Manual page 17

Notes
PES64H16G2 User Manual
®
Table 1.1 Initial Configuration Register Settings for PES64H16G2..................................................... 1-4
Table 1.2 PES64H16G2 Device IDs.................................................................................................... 1-6
Table 1.3 PES64H16G2 Revision ID................................................................................................... 1-6
Table 1.4 PCI Express Interface Pins.................................................................................................. 1-7
Table 1.5 Reference Clock Pins .......................................................................................................... 1-9
Table 1.6 SMBus Interface Pins .......................................................................................................... 1-9
Table 1.7 General Purpose I/O Pins.................................................................................................... 1-9
Table 1.8 System Pins....................................................................................................................... 1-13
Table 1.9 Test Pins............................................................................................................................ 1-16
Table 1.10 Power, Ground, and SerDes Resistor Pins ....................................................................... 1-16
Table 1.11 Pin Characteristics............................................................................................................. 1-18
Table 3.1 IFB Buffer Sizes................................................................................................................... 3-1
Table 3.2 EFB Buffer Sizes ................................................................................................................. 3-2
Table 3.3 Replay Buffer Storage Limit................................................................................................. 3-3
Table 3.4 Packet Ordering Rules in the PES64H16G2 ....................................................................... 3-5
Table 3.5 Conditions for Cut-Through Transfers ................................................................................. 3-7
Table 3.6 Request Metering Decrement Value.................................................................................. 3-11
Table 4.1 Initial Port Clocking Mode and Slot Clock Configuration State ............................................ 4-2
Table 5.1 PES64H16G2 Reset Precedence........................................................................................ 5-1
Table 5.2 Boot Configuration Vector Signals....................................................................................... 5-2
Table 5.3 Switch Mode Dependent Register Initialization ................................................................... 5-6
Table 7.1 Crosslink Port Groups........................................................................................................ 7-15
Table 7.2 Gen1 Compatibility Mode: bits cleared in training sets...................................................... 7-17
Table 8.1 SerDes Transmit Level Controls in the S[x]TXLCTL0 and S[x]TXLCTL1 Registers............ 8-5
Table 8.2 SerDes Transmit Driver Settings in Gen1 Mode.................................................................. 8-6
Table 8.3 SerDes Transmit Driver Settings in Gen2 Mode with -3.5dB de-emphasis ......................... 8-7
Table 8.4 SerDes Transmit Driver Settings in Gen2 Mode with -6.0dB de-emphasis ......................... 8-8
Table 8.5 Transmitter Slew Rate Settings ......................................................................................... 8-11
Table 8.6 PCI Express Transmit Margining Levels Supported by the PES64H16G2........................ 8-12
Table 8.7 SerDes Transmit Drive Swing in Low Swing Mode at Gen1 Speed .................................. 8-13
Table 8.8 SerDes Transmit Drive Swing in Low Swing Mode at Gen2 Speed .................................. 8-14
Table 9.1 Switch Routing Methods...................................................................................................... 9-1
Table 9.2 Downstream Port Interrupts................................................................................................. 9-2
Table 9.3 Downstream to Upstream Port Interrupt Routing Based on Device Number....................... 9-3
Table 9.4 Prioritization of ACS Checks for Request TLPs................................................................... 9-5
Table 9.5 Prioritization of ACS Checks for Completion TLPs.............................................................. 9-6
Table 9.6 TLP Types Affected by ACS Checks ................................................................................... 9-6
Table 9.7 Physical Layer Errors........................................................................................................... 9-7
Table 9.8 Data Link Layer Errors......................................................................................................... 9-7
Table 9.9 Transaction Layer Errors associated with the PCI-to-PCI Bridge Function ......................... 9-9
Table 9.10 Conditions Handled as Unsupported Requests (UR) by the PCI-to-PCI Bridge Function. 9-11
Table 9.11 Ingress TLP Formation Checks Associated with the PCI-to-PCI Bridge Function............. 9-11
Table 9.12 Egress Malformed TLP Error Checks ................................................................................ 9-12
Table 9.13 ACS Violations for Ports Operating in Downstream Switch Port Mode ............................. 9-13
Table 9.14 Prioritization of Transaction Layer Errors .......................................................................... 9-14
Table 10.1 Port Hot Plug Signals......................................................................................................... 10-3
Table 10.2 Negated Value of Unused Hot-Plug Output Signals .......................................................... 10-4
Table 11.1 PES64H16G2 Power Management State Transition Diagram .......................................... 11-2
Table 12.1 GPIO Pin Configuration ..................................................................................................... 12-1
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List of Tables
April 5, 2013