Operation - IBM RT Series Hardware Reference Manual

Operation
Data to be displayed is written into the 64K x 8 x 4 plane bit map memory by the system. This data
is then scanned out of the memory and sent as a serial video stream to the monitor.
The system processor can manipulate data residing in the bit map memory in several ways. The
choice of a particular,method is controlled by the type of instruction (Load or Store) and the
current value of a 2-bit mode field which resides within a 16-bit control register. The contents of
the control register must be initialized prior to the memory operation.
Hardware on the card allows data in the bit map to be manipulated without passing through a
processor. This hardware includes:
• A 16-bit write mask that enables write operations to individual bits
• A shifter that realigns bits before they are written to memory
• Data registers to hold data being processed
• Two 8-bit data mask registers that select bits being merged from data registers
• A logic unit that does all the actual merging.
Using this hardware, source data from either the system or from the bit map may replace or be
merged with data in the bit map. Images on the screen (in the bit map) can thus be moved,
inverted, overlaid, or replaced.
The adapter occupies two address ranges on the I/O channel. Sixteen bytes of I/O address space at
X '0150' through '015F' are used to load the data mask register, and the control registers. See the
section entitled "I/O Operations" on page 6 for specific register addresses and bit assignments.
The second address range occupied by the adapter is the bit map memory that consists of
128K-bytes starting at hex address 'D20000' in memory space on the I/O channel. When
addressing the bit map memory, the low order address bit must be
o.
Address bits A01 through
A16 are used to access memory. Address bit AOO is not used during memory accesses. This
restriction arises because the adapter allows word accesses to the bit map to begin on either even or
odd byte boundaries. Because the system restricts half -word accesses to even bytes, address lines to
the bit map memory are offset by one bit.
The most significant data byte of the I/O channel is written into or read from the bit map memory
location specified by the shifted address lines. The least significant data byte is written into or read
from the memory location specified by the shifted address lines increased or decreased by one in the
X or Y direction. The increase and decrease bits of the control register determine whether the
address is increased or decreased. The X and Y bits of the control register determine whether the X
or Y direction is changed.
As a result of the addressing scheme described above, each physical memory location in the bit map
can be accessed at either of two addresses. Access directly through the most significant byte, or
after the address bus has been increased or decreased, through the least significant byte.
Advanced Color Graphics Display Adapter 3