Programmable Baud-Rate Generator - IBM RT Series Hardware Reference Manual

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Bit 4
This bit is the opposite of the '-clear-to-send'
(-CTS) input. If bit 4 of the MCR loop is set to a
logical 1, this bit is equivalent to RTS of the MCR.
Bit 5
This bit is the opposite of the ' -data-set-ready ,
(-DSR) input. If bit 4 of the MCR is set to a logical
1, this bit is equivalent to DTR of the MCR.
Bit 6
This bit is the opposite of the '-ring-indicator'
(-RI) input.
If
bit 4 of the MCR is set to a logical 1 ,
this bit is equivalent to OUT 1 of the MCR.
Bit 7
This bit is the opposite of the '-data-carrier-detect'
(-DCD) input. If bit 4 of the MCR is set to a logical
1, this bit is equivalent to OUT 2 of the MCR.
Programmable Baud-Rate Generator
The controller has a programmable baud-rate generator that can
divide the clock input (1.8432 MHz) by any divisor from 1 to
655,535 or 2
1 6_1.
The output frequency of the baud-rate
generator is the baud rate multiplied by 16. Two 8-bit latches
store the divisor in a 16-bit binary format. These divisor latches
must be loaded during setup to ensure desired operation of the
baud-rate generator. When either of the divisor latches is loaded,
a 16-bit baud counter is immediately loaded. This prevents long
counts on the first load.
Serial/Parallel Adapter 17

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