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Description
This adapter has 36 RAM modules (128K x 1) for a total capacity
of 512Kb.
Memory Cycles
MEMR and MEMW commands require a l-wait-state, 3-clock
memory cycle. Data moves as a byte (8 data bits and 1 parity bit)
or as a word (16 data bits and 2 parity bits) and is parity-checked
on the adapter. A parity error causes an I/O channel check
(non-maskable interrupt) to the system.
Memory Address Switches
There are two banks of memory address switches on each
memory adapter. These switches are set to values for the first,
second, third, etc. memory adapter in the system. The following
figure shows the switch configuration for each adapter.
The first memory expansion adapter must start at address space
hex 100000.
If
more than one adapter is installed, no gaps
between memory are allowed. All expansion memory must be
one contiguous block starting at address hex 100000.
512KB Memory Expansion Option 1
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