IBM RT Series Hardware Reference Manual page 321

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TNL SN20-9844 (March 1987) to 75X0235
DEVICE
Y BIT
X WORD
DECODE
ADDRESS
ADDRESS
0
1/0
CHANNEL ADDRESS
1 1 0
1 1
o
0
Bits 7-16
Bits 17-22
o
718
15116
23
I
I
I
I
I
I
I
I
I
I
I
I
r
I
I
I
I
I
I
I
I
HORI
VER
ACCESS
T
H
/
000
V
0
I
I
I
I
WRITE
MASK
COUNT
Y BIT
ADDRESS
10 BITS
LOGIC
FUNC-
TION
71
8
I
I
I
I
I
I
Figure 3. I/O Channel DMA
X BIT
ADDRESS
4 BITS
15
I
I
I
I
Bits
Bits
Bits
X WORD
ADDRESS
10 BITS
MODE REGISTER
00
01-03
04-07
08-11
12-15
ARRAY X, Y ADDRESS
HORIZONTAL ACCESS BIT
RESERVED
WRITE MASK COUNT
LOGIC FUNCTION
START BIT DISPLACEMENT
Access to the bit map is controlled by specifying an even byte address via the I/O channel
address and the mode register contents. The mode register bits are set first via an I/O write
operation.
Extended Monochrome Graphics Adapter 9

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