IBM RT Series Hardware Reference Manual page 116

Bit 12
Bit 13
Bit 14
Bit 15
Bits 10 and 11 control whether the LSB of a bit map memory operation is accessed
from the left, right, above or below the MSB. See "Bit Map Memory Operations"
on page 5 for further explanation.
Block transfer
Bit 12 controls block transfer mode. When this bit is set from a 0 to ai, the
address of the next memory location accessed is stored in a pointer register on
the card. This address is adjusted to point at the next memory location at the
end of each memory cycle. That is, the X or Y address is increased or
decreased. After the first block transfer memory cycle has loaded the on-card
pointer register, the memory address supplied on the data bus is ignored, and
the pointer is used to access memory. To reload the pointer register, either
clear and set the block transfer bit again or read from the block transfer reload
I/O address, X'OI62'.
Interrupt enable
If bit 13 is 1, an interrupt is generated at the start of vertical sync.
If
this bit is
0, the interrupt is not generated. See "Interrupts" on page 9.
Sync enable (always 1)
Video enable
o
=
Disables video to monitor
1
=
Enables video to monitor
RAS Status Register (X'0160') Read Only
Bit
0 1
=
Even 0
=
Odd field
Bit 1 Horizontal sync toggle latch
Bit 2
Bit 3
Bit
4
o =
Vertical sync inactive 1
=
Vertical sync active
Serialized Video
1= X 0 = Y Stepping
Bit 5 1
=
Interrupt pending
Bit 6 0
=
Increase 1
=
Decrease the address counter
Bit 7
1
=
Enable load address
8 Advanced Monochrome Graphics Display Adapter