IBM RT Series Hardware Reference Manual page 442

Information about this register may be found under
"Programmable Baud Rate Generator" later in this section.
Interrupt Enable Register (Hex XF9):
This 8-bit register
allows the four types of controller interrupts to separately activate
the
I
chip-interrupt
I
(INTRPT) output signal. The interrupt
system can be totally disabled by resetting bits 0 through 3 of the
interrupt enable register (IER). Similarly, by setting the
appropriate bits of this register to logical 1, selected interrupts can
be enabled. Disabling the interrupt system inhibits the
I
IER
I
and the active
I
INTRPT
I
output from the chip. All other system
functions operate normally, including the setting of the line-status
and modem-status registers.
Interrupt Enlble Register (hex XF91
Bit 7 6 5 4 3 2 1 0
I I I
L> ''''",
D,ta A"U ....
''''~~
>
Enable Tx Holding Register
Empty Interrupt
>
Enable Receive Line Status
Interrupt
>
Enable Modem Status Interrupt
' - - - - - >
=0
' - - - - - - > = 0
' - - - - - - > = 0
' - - - - - - - > = 0
Interrupt Enable Register
Bit 0
Bit 1
Bit 2
Bit 3
Bits 4-7
When set to logical 1, enables the
received-data-available interrupt.
When set to logical 1, enables the
transmitter-holding-register-empty interrupt.
When set to logical 1, enables the receiver-line-status
interrupt.
When set to logical 1, enables the modem-status
interrupt.
These four bits are always logical O.
8 Serial/Parallel Adapter