IBM RT Series Hardware Reference Manual page 436

Address
Chip Select
-
- -
Controller
Address
Decode
...lIIo.
Register
-
Asynchronous
Communications
Bus
Select
Chip
Data Bus
--...
Interrupt
-
---
-
I
Oscillator
i
...
----.
--
1.8432 MHz
EIA
--...
--
Receivers
OIIIIIIL
g·Pin
OIIIIIIL EIA
-
-
-
--
Connector Drivers
Serial Portion Block Diagram
The serial portion of the adapter has a controller that provides the
following functions:
•
•
•
•
Adds or deletes standard, asynchronous-communications bits
to or from a serial data stream.
Provides full, double buffering, which eliminates the need for
precise synchronization.
Provides a programmable baud-rate generator.
Provides modem controls (CTS, RTS, DSR, DTR, RI, and
CD).
Communications Application
The serial output port may be addressed as either communications
port 1 or communications port 2 as defined by jumper J 1 (see the
following figure). In this section hex addresses begin with an X
which can be either a 3 for communications port 1 (interrupt level
4) or a 2 for communications port 2 (interrupt level 3).
2 Serial/Parallel Adapter