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Reset Register Format
Bit
7
6
5
4
3
2
1
0
Bit 0
Bit 1
IIIIIII~
Asynchronous Reset
Synchronous Res·et
Not Used
Asynchronous Reset-A logical 0 commands the
sequencer to asynchronous clear and halt. All
outputs are placed in the high impedance state
when this bit is a O. A logical 1 commands the
sequencer to run unless bit 1 is set to zero.
Resetting the sequencer with this bit can cause
data loss in the dynamic RAMs.
Synchronous Reset-A logical 0 commands the
sequencer to synchronous clear and halt. Bits 1
and 0 must both be ones to allow the sequencer
to operate. Reset the sequencer with this bit
before changing the Clocking Mode Register, if
memory contents are to be preserved.
Clocking Mode Register
This is a write-only register pointed to when the value in the
address register is hex 01. The output port address for this
register is hex 3C5.
Clocking Mode Register Format
Bit
7
6
5
4
3
2
1
0
8/9 Dot Clocks
Bandwidth
Shift Load
Dot Clock
Not Used
IBM Enhanced Graphics Adapter 19
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