IBM RT Series Hardware Reference Manual page 448

Bits 5-7
The controller's interrupt system can be tested by
writing to the lower six bits of the line status register
and the lower four bits of the modem status register.
Setting any of these bits to logical 1 generates the
appropriate interrupt (if enabled). Resetting these
interrupts is the same as for normal controller
operation. To return to normal operation, the
registers must be reprogrammed for normal
operation, and then bit 4 of the MeR must be reset
to logical O.
These bits are permanently set to logical O.
Line Status Register (Hex XFD):
This 8-bit register provides
the processor with status information about the data transfer.
Line Stltus Register Ihex XFDI
Bit 7 6 5 4 3 2 1 0
~>o'm~~Y
>
Overrun Error
>
Parity Error
>
Framing Error
>
Break Interrupt
>
Transmitter Holding Register
Empty
>
Tx Shift Register Empty
>
=0
Line Status Register
Bit 0 This bit is the receiver data ready (DR) indicator. It
is set to logical 1 whenever a complete incoming
character has been received and transferred into the
receiver buffer register. Bit 0 may be reset to logical
o
by the processor either reading the data in the
receiver's buffer register or writing logical 0 in it.
Bit 1 This bit is the overrun error (OE) indicator. It
indicates that data in the receiver's buffer register
was not read by the processor before the next
character was transferred into the register, thereby
destroying the previous character. The OE indicator
is reset whenever the processor reads the contents of
the line status register.
14 Serial/Parallel Adapter