IBM RT Series Hardware Reference Manual page 340

TNL SN20-9844 (March 1987) to 75X0235
Video Enable (bit 4)
This bit, when active, indicates that video data from the bit map is being
supplied to the monitor. If the bit is inactive, the video data from the bit map
is not being supplied to the monitor. The video enable signal is manipulated
via graphic operation types and I/O commands. The video enable signal
should be activated after a POR or a reset adapter command.
Black on White Background (bit 5)
When active, inverts all video data going from the bit map to the video drive
circuits. This gives an effect of a white background. Thus a clear screen
operation (set bit oft) or a disable video turns the screen white. When this bit
is inactive, a white on black background is displayed. Therefore an off pel in
the bit map corresponds to an off pelon the screen and the disabled video
turns the screen black.
Horizontal Sync (bit 6)
This bit is for diagnostics and indicates the horizontal cycle is working.
Increment Queue Counter Register (Address X'OD14')
This is a write only register and the data is of no significance. A write to this register increments
the command queue counter by one. The graphic operation processor decrements the queue
counter with a flag bit in the execute command word. The graphic operation processor polls the
queue counter to see if any graphic operations are pending execution on the queue. If the queue
counter is not zero, processing of the queue begins or continues. The maximum number of
increments before a decrement occurs is 1023. If count is incremented past 1023, then 1024
graphic operations queue loads are not executed.
Disable Video Data Output (Address X'ODIA')
A read operation from this I/O address disables the adapter video data output.
Enable Video Data Output (Address X'ODIA')
A write operation to this I/O address enables the adapter video data output to the monitor. Data
written to this address is ignored.
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Extended Monochrome Graphics Adapter