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Line Status Register
This 8-bit register provides status information to the processor about the data transfer. The
contents of the line status register are described below:
Line Status Register
(Hex Address n235, n230, n245 )
Bit
7
6
5
4
3
2
1
a
I
lS
Data ready
Overrun error
Parity error
-
Framing error
...
--
Break interrupt
-
-
Transmitter holding
---
register empty
..
Tx shift register empty
- -
=
a
...
Bit 0
This bit is the receiver data ready (DR) indicator. Bit 0 is set to a logicall whenever a
complete incoming character has been received and transferred into the receiver buffer
register. Bit 0 may be reset to a logical 0 either by the processor reading the data in
the receiver buffer or by writing a logical 0 into it from the processor.
Bit 1
This bit is the overrun error (OE) indicator. Bit 1 indicates that data in the receiver
buffer register was not read by the processor before the next character was transferred
into the receiver buffer register, and thereby destroyed the previous character. The OE
indicator is reset whenever the processor reads the contents of the line status register.
Bit 2
This bit is the parity error (PE) indicator. Bit 2 indicates that the received data
character does not have the correct even or odd parity as selected by the even parity
select bit. The PE bit is set to a logical 1 whenever a parity error is detected and is
reset to a logical 0 whenever the processor reads the contents of the line status register.
Bit 3
This bit is the framing error (FE) indicator. Bit 3 indicates that the received character
does not have a valid stop bit. Bit 3 is set to a logical 1 whenever the stop bit following
the last data bit or parity is detected as a zero bit (spacing level).
Bit 4
This bit is the break interrupt (BI) indicator. Bit 4 is set to a logicall whenever the
received data input is held in the spacing (logical 0) state for longer than a full word
transmission time (that is, the total time of start bit
+
data bits
+
parity
+
stop bits).
20
5080 Peripheral Adapter
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