IBM RT Series Hardware Reference Manual page 445

Ulle C.lllni He,lller (hex XFBI
Bit 7 6 5 4 3 2 1 0
~
Wod "oglh S,',,' BI' 0
>
Word Length Select Bit 1
>
Number 01 Stop Bits
>
Parity Enable
>
Even Parity Select
>
Stuck Parity
>
Set Break
>
Divisor Latch Access Bit
Line Control Register
Bits 0, 1 These two bits specify the number of bits in each
serial character that is sent or received. The
encoding of bits 0 and 1 is as follows:
Bit 1 Bit2 Word Length (Bits)
0 0 5
0
1
6
1 0
7
1 1 8
Word length
Bit 2 This bit specifies the number of stop bits in each
serial character that is sent or received. If bit 2 is a
logical 0, one stop bit is generated or checked in the
data sent or received. If bit 2 is logical 1 when a
5-bit word length is selected through bits 0 and 1,
1-1/2 stop bits are generated or checked. If bit 2 is
logical 1 when either a 6-, 7-, or 8-bit word length
is selected, two stop bits are generated or checked.
Bit 3 This bit is the parity-enable bit. When bit 3 is
logical 1 , a parity bit is generated (transmit data) or
checked (receive data) between the last data word
and stop bit of the serial data. (The parity bit is
used to produce an even or odd number of 1 's when
the data-word bits and parity bit are summed.)
Bit 4 This bit is the even-parity-select bit. When bit 3 is
a logical 1 and bit 4 is a logical 0, an odd number of
Serial/Parallel Adapter 11