IBM RT Series Hardware Reference Manual page 449

Bit 2 This bit is the parity error (PE) indicator and
indicates the received data character does not have
the correct even or odd parity, as selected by the
even-parity-select bit. The PE bit is set to logical 1
upon detection of a parity error, and is reset to
logical 0 whenever the processor reads the contents
of the line status register.
Bit 3 This bit is the framing error (FE) indicator. It
indicates the received character did not have a valid
stop bit. Bit 3 is set to logical 1 whenever the stop
bit following the last data bit or parity bit is detected
as a zero bit (spacing level).
Bit 4 This bit is the break interrupt (BI) indicator. It is set
to logical 1 whenever the received data input is held
in the spacing state (logical 0) for longer than a
full word transmission time (that is, the total time of
start bit
+
data bits
+
parity stop bits).
Note: Bits 1 through 4 are error conditions that
produce a receiver line-status interrupt whenever
any of the corresponding conditions are detected.
Bit 5 This bit is the transmitter holding register empty
(THRE) indicator. It indicates the controller is
ready to accept a new character for transmission. In
addition, this bit causes the controller to issue an
interrupt to the processor when the TRHE interrupt
enable is set active. The THRE bit is set to logical 1
when a character is transferred from the transmitter
holding register into the transmitter shift register.
It
is reset to logical 0 when the processor loads the
transmitter holding register.
Bit 6 This bit is the transmitter empty (TEMT) indicator.
It is set to logical 1 whenever the transmitter holding
request (THR) and the transmitter shift request
(TSR) are both empty. It is reset to logical 0
whenever THR or TSR contains a data character.
Bit 7 This bit is permanently set to logical O.
Serial/ParaDel Adapter 15