IBM RT Series Hardware Reference Manual page 441

Receiver Buffer Register (bex XF81
Bit 7 6 5 4 3 2 1 0
~>Da~mtO
>
Data Bit 1
>
Data Bit 2
>
Data Bit 3
>
Data Bit 4
>
Data Bit 5
>
Data Bit 6
>
Data Bit 7
Receiver Buffer Register
Bit 0 is the least-significant bit and the first bit received serially.
Divisor Latch LSD (Hex XF8)
Divisor Latch leISt Slgnlflclnt Bit (blx XF81
Bit 7 6 5 4 3 2 1 0
~>mtO
>
Bit 1
>
Bit 2
>
Bit3
>
Bit4
>
Bit 5
>
Bit6
>
Bit 7
Divisor Latch Least Significant Bit
Information about this register may be found under
"Programmable Baud Rate Generator" later in this section.
Divisor Latch MSD (Hex XF9)
Divisor Lltch Most SlgnlflClnt Bit (hex XF91
Bit
7 6 5 4 3 2 1 0
~>.tO
>
Bit1
>
Bit2
>
Bit3
>
Bit4
>
Bit5
>
Bit 6
>
Bit 7
Divisor Latch Most Significant Bit
Serial/Parallel Adapter 7