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System Read Operation (Mode
=
XX)
This operation reads 16 bits of data from the bit map memory and places it on the system data bus.
Onboard data latches D 1, D2, and D3 are updated by this operation. Data is loaded into latches
Dl, D2, and D3 regardless of the setting of the mode. However, valid data is returned to the system
processor only
if
the mode is '00'. Data returned to the system is from the lowest numbered plane
that is enabled for reading.
Automatic Read/Write Operation (Mode
=
11)
In this mode of operation, data is alternately read into D 1, D2 and D3 and then written to memory
with successive write operations from the microprocessor. Data read from memory is not gated
onto any busses external to the data path, but is used only to update D 1, D2, and D3. This allows
the fast 'Store' operation to be used for block transfer operations with no 'Loads' required.
To get the alternate read/write operations into phase with the source and destination addresses, the
system processor should do a 'Load' operation from the first source address. Subsequent 'Stores'
will automatically alternate between read and writes to the bit map.
110 Operations
To manipulate the various registers on the adapter, a set of I/O operations are required.
Data Mask Register (X'OI52') Write Only
Typically these two 8-bit registers (DMI and DM2) are initialized with data representing the
inverse of each other, and are used to mask the bits on or off for logical combination through the
logic unit.
•
An 8 bit for DMI Mask (Data Bus MS Byte, bits 0-7)
•
An 8 bit for DM2 Mask (Data Bus LS Byte, bits 0-7).
6
Advanced Color Graphics Display Adapter
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