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Bit 0
Bit 1
Bit 2
Bit 3
8/9 Dot Clocks-A logical 0 directs the
sequencer to generate character clocks 9 dots
wide; a logical 1 directs the sequencer to generate
character clocks 8 dots wide. Monochrome
alphanumeric mode (07H) is the only mode that
uses character clocks 9 dots wide. All other
modes must use 8 dots per character clock.
Bandwidth-A logical 0 makes CRT memory
cycles occur on 4 out of 5 available memory
cycles; a logical 1 makes CRT memory cycles
occur on 2 out of 5 available memory cycles.
Medium resolution modes require less data to be
fetched from the display buffer during the
horizontal scan time. This allows the CPU
greater access time to the display buffer. All high
resolution modes must provide the CRTC with 4
out of 5 memory cycles in order to refresh the
display image.
Shift Load-When set to 0, the video serializers
are reloaded every character clock; when set to 1,
the video serializers are loaded every other
character clock. This mode is useful when 16 bits
are fetched per cycle and chained together in the
shift registers.
Dot Clock-A logical 0 selects normal dot clocks
derived from the sequencer master clock input.
When this bit is set to 1, the master clock will be
divided by 2 to generate the dot clock. All the
other timings will be stretched since they are
derived from the dot clock. Dot clock divided by
two is used for 320x200 modes (0, 1, 4, 5) to
provide a pixel rate of 7 MHz, (9 MHz for mode
D).
Map Mask Register
This is a write-only register pointed to when the value in the
address register is hex 02. The output port address for this
register is hex 3C5.
20 IBM Enhanced Graphics Adapter
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