IBM RT Series Hardware Reference Manual page 112

I
0000 0001 0002
0003 - 0058 0059
005A
005B - 007E
007F
0080 0081 0082 0083 - 0008 0009 OODA
OODB - OOFE
OOFF
512
Sean
Lines
L
FF80 FF81 FF82
FF83 - FFD8 FFD9
FFDA
FFDB - FFFE
FFFF
90 Bytes Visible Memory
...
I~
38 Bytes Hidden Memory
128 Bytes Total Bit Map Memory Width
Figure 2.
Bit Map Memory Addresses
The mapping between the physical addresses shown in Figure 2 and denoted as 'P' in the equations
and the I/O channel address denoted as 'C' in the equations shown as follows for each of the
increase and decrease bits and the X and Y status bits.
Word Storage Location
I/O Channel Inc/Dec X/V Physical to I/O Channel to Physical
Byte I/O Channel to Physical
MS Byte either either
C=2P
=>
P=C/2
LS Byte
+
X
C=2P-2
=>
P=C/2 +1
LS Byte X
C=2P+2
=>
P=C/2 -1
LS Byte
+
Y C=2P-256
=>
P=C/2
+128
LS Byte
y
C=2P+256
=>
P=C/2 -128
Figure 2 shows how on-card physical memory byte addresses are mapped to the display screen.
The bits in each byte are shifted onto the screen with the most significant bit to the left.
4 Advanced Monochrome Graphics Display Adapter