IBM RT Series Hardware Reference Manual page 103

The mapping of the most significant byte, bits 0-5 to output colors, is as follows:
Most Significant Byte
Pel Color 0
1
2 3 4 5
Low Intense red 1 0
0 0
0 0
Med
Intense red
0
1 0
0
0 0
High Intense red 1 1 0 0 0 0
Low Intense green 0 0 1 0 0 0
Med Intense green
0
0
0
1 0
0
High Intense green 0 0 1 1 0 0
Low Intense Blue 0 0 0 0 1 0
Med Intense blue
0
0 0
0
0 1
High Intense blue 0 0 0 0 1 1
Other combinations of the three basic colors described above produce alternate hues.
Block Transfer Reload (X'0152') Read Only
Reading from this I/O location loads the address of the next memory access into the on-card
address pointer register. No significant data is returned when this location is read. See "Data
Control Register (X'0150') Write Only" on page 7 for more information regarding the use of this
I/O command.
Interrupts
The adapter generates a level 11 interrupt at the start of vertical sync if bit 13 (interrupt enable) of
the control register is a 1. This interrupt will not occur if bit 13 is a O. When the adapter generates
an interrupt, bit 5 of the RAS status register is set to 1. To clear bit 5 and reenable level 11
interrupts, an output to hex 6F3 with any data value must be issued. Interrupt ·11 is a shared
interrupt.
Advanced Color Graphics Display Adapter 11