Lexicon RV-8 Service Manual page 120

RV-8 Service Manual
S/PDIF IO (Sheet 13)
The AVRX FPGA receives eight S/PDIF streams from the back panel. Four are from coaxial sources
requiring signal conditioning and amplification. The remaining four are from optical sources that go
directly to the FPGA. Record S/PDIF outputs are available as a single coax and a single optical signal.
This page also illustrates the Zone 3 video output.
Coax S/PDIF Inputs
J1 and J2 are dual stacked RCA connectors. Each input is protected by a spark gap, providing a path for
ESD discharges made to the connectors. C1/R1, C3/R2, C5/R3, and C7/R4 present a standard
impedance to the incoming S/PDIF signals. C2, C4, C6, and C8 provide AC de-coupling for each of the
signals as they enter the amplifier stage.
D1-D4 provide diode clamp protection of the amplifiers by ensuring that the input stages are never
subjected to voltages greater than 5V nor lower than DGND. U3 and U4 are configured as amplifiers by
R5-R12 by forcing the gates to run in a semi-linear region. The effective result is that each input gate acts
as an amplifier with a gain of 10, increasing the amplitude of the input stream from 0.5V to 5V. The
second gate in the signal chain acts as a simple buffer, providing a minimal load to the amplifier stage
thereby preserving stability.
Optical S/PDIF Inputs
CP1-CP4 are standard TORX style optical receivers. No additional signal conditioning is required for
these signals, and as such they are presented to the AVRX FPGA right from these inputs.
Record Zone S/PDIF Outputs
A digital audio output for the Record Zone is sourced from the AVRX FPGA to a 74VHCT244 Octal Buffer
U2. Two out of the available eight buffers are actually used. The first output drives a TORX style optical
output connector. The second buffer output drives a voltage divider that reduces the CMOS level of the
signal to one of approximately 1.2V in amplitude. C18 and C19 provide wave shaping and impedance
compensation to the signal before being output through RCA coax connector J8. This output network
conditions the CMOS signal to standard S/PDIF specifications. J8 is protected from ESD by a spark gap.
Zone 3 Composite Video Output
J7 accepts a composite video signal from the Video Board and passes it to the outside world. J7 is spark
gap protected.
Trigger Outputs (Sheet 14)
The RV-8 provides two 12V voltage sources for remote powering external accessories in the user's
DC
B B
home theater. Each trigger output can provide up to 1 Amp to an external load.
U8 is a low drop-out adjustable regulator. It is powered by +15V while it's output voltage is set by R15 and
R16, following the equation:
V = 1.275[(R15 + R16) / R15]
O
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C25 provides local bulk capacitance for the voltage input. C22 is a low ESR type capacitor which provides
stability for the regulator and bulk capacitance for the output voltage. R13 and R14 provide a current path
for any load that would source current when shut off, as U8 cannot sink current. FB1 and C10 provide
suppression of high frequencies, preventing EMI effects. J3 is the output connector which is protected by
a spark gap.
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