Lexicon RV-8 Service Manual page 194

8 7
D
CPU_VIDTUNIRQ/
[2/D7]
CPUCLKOUT
[9/C8]
R118
205
1%
R119
C118 C117
3K
470PF .1/25
CPUCLKI
[7/B3]
NC
+5VD
10K
R114
CPUDATA15
CPUDATA14
CPUDATA13
CPUDATA12
C
CPUDATA11
CPUDATA10
CPUDATA9
CPUDATA8
CPUDATA7
CPUDATA6
CPUDATA5
CPUDATA4
CPUDATA3
CPUDATA2
CPUDATA1
CPUDATA0
FB14
BROWN_OUT
[12/A4]
CPU_CRYIRQ/
[2/D7]
CPU_DSPABIRQ/
[2/D7]
CPU_KYBDIRQ/
[2/D7]
FAN_DRV
[17/A6]
FPGA_INIT/
[9/D8]
FPGA_PROG/
[9/D8]
FPGA_DONE
[9/D2,10/D8]
TEMP7
TEMP6 R127 0
TEMP5 R126 0
SPARE_AD 0
R125
[12/A8]
TEMP4 0
R124
TEMP3 0
B R123
TEMP2 0
R122
TEMP[7:1]
TEMP1 0
R121
[12/B8]
FPGA_SDATA
[9/D2]
OVLED
[12/A8]
SYSLED
[12/A8]
FP_IR_ACK
[12/B6]
NC
NC
6 8
10K 10K
RP13 RP13
3 1
5 7
R117
10K 10K
10K
RP13 RP13 *
4 2
+5VD
FPGA_CCLK
E6 [9/D2]
C114
R110
TL7705B
C111 1.2K
A .1/25
R113
1 8
REF VCC
1.2K
.1/25
2 7
RESIN SENSE
C112
R111
3 6
CT RESET
1.2K
.1/25
4 5
GND RESET R112
1.2K
U31
T=(CT*1.3*10000)
= 1.3mS
8 7
6
RP11
8 1 CPUADDR20
10K
RP11
7 2 CPUADDR19
10K CPUADDR1
RP11
CPUADDR2
6 3 CPUADDR18
CPUADDR3
10K CPUADDR4
CPUADDR5
CPUADDR6
CPUADDR7
CPUADDR8
+5VD +5VD
CPUADDR9
CPUADDR10
R120
83
PA15_CK
80 35
PLLVCC WDTOVFN 47
81 NC
PLLCAP
82 32
PLLVSS PB9_IRQ7N_A21
31 CPUADDR20
PB8_IRQ6N_A20_WAITN
30 CPUADDR19
PB7_A19
29 CPUADDR18
PB6_A18
74 22 CPUADDR17
EXTAL A17
72 20 CPUADDR16
XTAL A16
19 CPUADDR15
A15
18 CPUADDR14
A14
17 CPUADDR13
A13
16 CPUADDR12
SH7014
A12
15 CPUADDR11
A11
52 14 CPUADDR10
D15 A10
53 13 CPUADDR9
D14 A9
54 12 CPUADDR8
D13 A8
56 11 CPUADDR7
D12 A7
57 10 CPUADDR6
D11 A6
58 9 CPUADDR5
D10 A5
59 8 CPUADDR4
D9 A4
60 7 CPUADDR3
D8 A3
62 6 CPUADDR2
D7 A2
63 5 CPUADDR1
D6 A1
64 4 CPUADDR0
D5 A0
66
D4
67 44
D3 PA7_TCLKB_CS3N
68 45
D2 PA6_TCLKA_CS2N
69 40 PROGCS/
D1 CS1N
70 41 BOOTCS/
D0 CS0N
76 34
NMI RDN
42 36
PA9_TCLKD_IRQ3N WRHN
43 38
PA8_TCLKC_IRQ2N WRLN
46
PA5_IRQ1N_SCK1
49 28
PA2_IRQ0N_SCK0 PB5_IRQ3N_RDWR
24
PB2_IRQ0N_RASN
89 26
PE4_TIOC1A PB4_IRQ2N_CASHN
102 25
PE5_TIOC1B PB3_IRQ1N_CASLN
104
PE6_TIOC2A
105 1 FLBY/
PE7_TIOC2B PE14_DACK0N_AHN
85
PE0_TIOC0A_DREQ0N
99 86
PF7_AN7 PE1_TIOC0B_DRAK0
98 87
PF6_AN6 PE2_TIOC0C_DREQ1N
96 88
PF5_AN5 PE3_TIOC0D_DRAK1
95 2
PF4_AN4 PE15_DACK1
94
PF3_AN3
93 51
PF2_AN2 PA0_RXD0
92 50
PF1_AN1 PA1_TXD0
91 48
PF0_AN0 PA3_RXD1
47
PA4_TXD1
112
PB13
111 73
PE12 MD3
110 75
PE11 MD2
108 78
PE10 MD1
107 79
PE9 MD0
106
PE8
84
RES
U33
4
RP11
10K
5
6
5 4
AT49C1024
+5VD
CPUADDR1 24
A0
CPUADDR2 25
DRAM A1
CPUADDR3 26
17 21 A2
A0 VCC CPUADDR4 27
18 6 A3
A1 VCC CPUADDR5 28
19 1 A4
A2 VCC CPUADDR6 29
20 A5
A3 CPUADDR7 30
23 A6
A4 CPUADDR8 31
24 A7
A5 CPUADDR9 32
25 A8
A6 CPUADDR10 35
26 2 CPUDATA0 A9
A7 D0 CPUADDR11 36
27 3 CPUDATA1 A10
A8 D1 CPUADDR12 37
28 4 CPUDATA2 A11
A9 D2 CPUADDR13 38
NC 16 5 CPUDATA3 A12
NC D3 CPUADDR14 39
NC 15 7 CPUDATA4 A13
NC D4 CPUADDR15 40
8 CPUDATA5 A14
D5 CPUADDR16 41
13 9 CPUDATA6 A15
WE D6
14 10 CPUDATA7
RAS D7 43
29 33 CPUDATA8 WE
OE D8 22
30 34 CPUDATA9 OE
UCAS D9 BTFLCS/ 3
31 35 CPUDATA10 CE
LCAS D10
36 CPUDATA11
D11 12
NC 11 38 CPUDATA12 VSS1
NC D12 34
NC 12 39 CPUDATA13 VSS2
NC D13
40 CPUDATA14
D14
22 41 CPUDATA15
GND D15
37 32 NC
GND NC
42
GND
EMULATOR
60NS
+5VD
1MX16 1
A17
ROMUCS/ 2
U42
CS
CPUDATA15 3
D15
CPUDATA14 4
JUMPER SELECT D14
CPUDATA13 5
R83 R85
D13
1-2: BOOT FLASH CPUDATA12 6
* *
D12
10K
2-3: ROMULATOR 10K CPUDATA11 7
W5
D11
1 CPUDATA10 8
D10
2 CPUDATA9 9
+5VD
D9
3 CPUDATA8 10
*
D8
11
GND1
W3 CPUDATA7 12
D7
R116 R115
CPUDATA6 13
*
D6
CPUDATA5 14
10K
10K D5
CPUDATA4 15
D4
CPUDATA3 16
D3
CPUDATA2 17
D2
CPUDATA1 18
D1
CPUDATA0 19
D0
20
OE
[1/B3]
CPUADDR20 9
A19
CPUADDR19 16
A18
CPUADDR18 17
A17
CPUADDR17 48
A16
CPUADDR16 1
A15
CPUADDR15 2
A14
CPUADDR14 3
A13
CPUADDR13 4
A12
CPUADDR12 5
A11
CPUADDR11 6
A10
CPUADDR10 7
A9
CPUADDR9 8
A8
CPUADDR8 18
A7
CPUADDR7 19
A6
CPUADDR6 20
A5
CPUADDR5 21
A4
CPUADDR4 22
A3
CPUADDR3 23
A2
CPUADDR2 24
A1
CPUADDR1 25
A0
14
WP
11
WE
26
CE
28
OE
+5VD 12
RESET
46
VSS1
R82
27
R84
VSS2
W4 0
1 10K
2
3
*
5 4
3
CPUADDR[20:0]
[7/B5,9/C7]
CPUDATA[15:0]
[2/D7,7/A5]
+5VD
44
VCC
21 CPUDATA0
IO0
20 CPUDATA1
IO1
19 CPUDATA2
IO2
18 CPUDATA3
IO3
17 CPUDATA4
IO4
16 CPUDATA5
IO5
15 CPUDATA6
IO6
14 CPUDATA7
IO7
11 CPUDATA8
IO8
10 CPUDATA9
IO9
9 CPUDATA10
IO10
8 CPUDATA11
IO11
7 CPUDATA12
IO12
6 CPUDATA13
IO13
5 CPUDATA14
IO14
+5VD
4 CPUDATA15
IO15
1 NC
NC1
2 NC
NC2
13 NC
NC3
33 NC
R153
NC4
42 NC
*
NC5
23 NC 10K ADDR20 ADDR19
DC
*
U32
+5VD CPUADDR20
CPUADDR19
40
VCC
39 CPUADDR18
WT
38 CPUADDR17
A16
37 CPUADDR16
A15
36 CPUADDR15
A14
35 CPUADDR14
A13
34 CPUADDR13
A12
33 CPUADDR12
A11
32 CPUADDR11
A10
31 CPUADDR10
A9
30
GND2
29 CPUADDR9
A8
28 CPUADDR8
A7
27 CPUADDR7
A6
26 CPUADDR6
A5
25 CPUADDR5
A4
24 CPUADDR4
A3
23 CPUADDR3
A2
22 CPUADDR2
A1
21 CPUADDR1
A0
*
J14
CPUCS3/
[7/B5]
CPUCS2/
[2/C7,9/C8]
CPURDWR
CPUWRL/
[7/B5,9/C8]
CPUWRH/
[7/B5]
CPURD/
[7/B5,9/C8]
AM29F160
+5VD
+5VD
R132
37
VCC
10K
47
BYTE
15 FLBY/
RYBY [1/B5]
45 CPUDATA15
DQ15_A-1
43 CPUDATA14
DQ14
41 CPUDATA13
DQ13
39 CPUDATA12
DQ12
36 CPUDATA11
DQ11
34 CPUDATA10
DQ10
32 CPUDATA9
DQ9
30 CPUDATA8
DQ8
44 CPUDATA7
DQ7
42 CPUDATA6
DQ6
40 CPUDATA5
DQ5
38 CPUDATA4
DQ4
35 CPUDATA3
DQ3
33 CPUDATA2
DQ2
31 CPUDATA1
DQ1
29 CPUDATA0
DQ0
+5VD
10 NC
NC1
13 NC
NC2
1M X 16
120NS R81
U26 10K
BOOT_LOCK
[2/A7]
DEBUG_RXD
[12/D8]
DEBUG_TXD
[12/D8]
USER_RXD
[12/C8]
USER_TXD
[12/C8]
RESET/
[2/C7]
RESET
[12/D4]
CPU_WRDCLK_MON
[2/D7]
FPSWITCH1
[12/A6]
FPSWITCH2
[12/A6]
FPSWITCH3
[12/A6]
3
2 1
REVISIONS
DRAFTER Q.C.
REV DESCRIPTION
CHECKER AUTH.
RWH CW
1 CHANGED PER DCR 020913-00
11/05/02 12/20/02
CAM MAG
11/06/02 12/20/02
RWH CW
2 CHANGED PER DCR 030307-00
5/2/03 5/20/03
CAM MAG
5/14/03 5/20/03
RWH CW D
3 CHANGED SHT. 12 PER DCR 030307-00-A
5/22/03 5/22/03
CAM MAG
5/22/03 5/22/03
RWH ECM
4 CHANGED PER DCR 030626-00
9/29/03 10/9/03
CAM MAG
10/2/03 10/9/03
RWH CW
5 CHANGED SHTS 1,3,12 PER DCR 031124-00
12/2/03 12/30/03
CAM MAG
12/8/03 12/30/03
RWH CW
6 CHANGED SHTS 7 & 19 PER ECO 040422-00
4/27/04 4/29/04
CAM KAB
4/29/04 5/2/04
NOTES
1 UNLESS OTHERWISE INDICATED, RESISTORS ARE 1/10W
C
2 UNLESS OTHERWISE INDICATED, RESISTORS ARE 5%
3 UNLESS OTHERWISE INDICATED, CAPACITORS ARE UF/V
4 DIGITAL ANALOG CHASSIS POWER
GROUND GROUND GROUND GROUND
5 [XX/XX] DENOTES [SHEET NUMBER/SECTOR]
6 LAST REFERENCE DESIGNATORS USED: C178, CP5, D49, FB18, J32, L3, Q2,
R188, RP37, U48, W10, Y2.
*
7 COMPONENTS MARKED WITH ARE NOT ON BOM.
DOCUMENT CONTROL BLOCK: #060-15559
SHEET REVISION TITLE
1 OF 19 6 HOST PROCESSOR
2 OF 19 3 BUFFERS, LEVEL SHIFTERS
3 OF 19 4 DSP HOST 1 AND 2
4 OF 19 3 DSP A SDRAM AND FLASH
5 OF 19 3 DSP B EXTERNAL MEMORY
6 OF 19 3 DSP SPI, SERIAL, AND LINK PORTS
7 OF 19 4 DSP/FPGA POWER CONN.
8 OF 19 3 CRYSTAL DSP
9 OF 19 3 MAIN FPGA
10 OF 19 3 FPGA FLASH
B
11 OF 19 3 EXPANSION PORT SERIES TERMINATIONS
12 OF 19 5 BOARD INTERCONN/DEBUG
13 OF 19 3 SPDIF I/O
14 OF 19 3 TRIGGER OUTPUTS
15 OF 19 3 VCO A
16 OF 19 3 VCO B
17 OF 19 3 POWER SUPPLY
18 OF 19 3 IR REMOTE CONNECTOR
19 OF 19 4 BYPASS CAPACITORS
© 2004 HSG
A
CONTRACT
exicon
3 OAK PARK
NO.
BEDFORD, MA 01730
TITLE
APPROVALS DATE
SCHEM, MAIN BD,RV8
DRAWN
RWH 4/26/02
HOST PROCESSOR
CHECKED
SIZE CODE NUMBER REV
CAM 4/30/02
B
6
060-15559
Q.C.
CW 5/1/02
FILE NAME
ISSUED
JV 4/30/02 15559-6 . 1 SHEET 1 OF 19
2 1