Lexicon RV-8 Service Manual page 115

Lexicon
Expansion Slots
Signals: EXP[17:0]
The RV-8 has built in capacity for future expansion capabilities. A general purpose 18-bit bus is shared
between two expansion ports. To date, the only use for this expansion bus is for a test fixture that may be
plugged into either port to test continuity of the signals to the FPGA. Beyond this, there are no clear
definitions of signal function for this bus.
FPGA Flash (Sheet 10)
This page contains the configuration FLASH EPROM for the AVRX FPGA, FPGA configuration indicator,
the audio reference clock generator, and the Expansion slot connectors.
Configuration FLASH EPROM (U40)
This device is a Xilinx XC18V02 2Mbit 3.3V EPROM that is used to store programming algorithms for the
AVRX FPGA. It is packaged in a 44-pin PLCC package. This device is used only during development
cycles, and as such is not installed on the Main Board under normal circumstances. In order to use the
FLASH as illustrated, the AVRX FPGA must be placed in Master Serial Mode; see the Configuration
section on page 6-30 for further details as to how to implement this operational mode.
In Master Serial Mode, the FPGA provides an active low reset signal to the EPROM via XFLASH_INIT/
which resets the internal address counter of the EPROM to zero. The FPGA then asserts this reset signal
high. Once the reset signal is high, the FPGA asserts the EPROM chip select low via FPGA_DONE. The
FPGA then provides a clock signal to the EPROM via XFLASH_CCLK, which causes serial data to be
shifted out of the D0 data pin into the FPGA DIN pin; this signal is called XFLASH_DIN on the schematic.
When configuration has completed, the FPGA re-asserts FPGA_DONE high. This signal is inverted by a
single gate inside U38 causing D46 to illuminate upon completion of the configuration operation. This
provides a visual cue as to when the FPGA is done.
XFLASH_CF/ is an output pin from the EPROM that allows the programming port connected to the
EPROM to configure the FPGA.
Programming Ports
Signals: JTAG_TCK, JTAG_TDO, JTAG_TDI, JTAG_TMS
The EPROM supports boundary scan testing as well as In Circuit Programming via a fully compliant IEEE
1149.1 JTAG Port. J16 is a 1x9 row of pins that can accept a Xilinx download cable. By configuring the
FPGA in Slave Serial Mode, J15 may be used as an In Circuit Programming port that will directly
configure the FPGA, bypassing the EPROM.
Typically during development, the EPROM is socketed for easy removal and insertion and the EPROM is
programmed in a standard PROM programmer.
Audio Reference Clock (U35)
AUDIO_OSC is a reference signal that is used by the PLL phase comparators within the AVRX device. It
is used as a reference when no sample clock is derived from the S/PDIF inputs. U35 is a standard
Unbuffered Hex Inverter of which one stage is configured as a Colpitts Oscillator comprised of Y1, R145,
C140, and C141. This circuit generates a 14.112MHz square wave. R145 provides hysteresis for the
gate, initiating and sustaining a reliable switching characteristic, while C140 and C141 provide the proper
AC load to the reactive element of Y1. The second stage of this circuit is another gate from the hex
package that simply buffers the output of the oscillator, presenting a minimal load to it while providing
drive capability. R147 provides source impedance matching to the characteristic impedance of the PCB.
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