Lexicon RV-8 Service Manual page 110

RV-8 Service Manual
to the SPI DMA Block Size Register. Once this register is written, then a SPI transfer occurs to the
SHARC. When the transfer is done, the host CPU is interrupted by DSPABIRQ/. The system software
must then clear bit 4 in the SPI Chip Select Register to zero.
DSPBSEL/ is the chip select for the SPI port on SHARC2 (U37). This chip select is enabled by writing a
one to bit 5 in the SPI Chip Select Register. Transfers to SHARC2 are implemented in the same fashion
as described under DSPASEL/.
DSPASP3FPGA is the DOWNMIX audio return signal from SHARC1 in SPORT format. The data present
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in this stream is converted to S/PDIF and I S formats and mapped via Look-Up Table to the output ports.
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SPORT_CLK_A is the serial shift clock for the data present on DSPASP3FPGA and DSPASP0FPGA.
SPORT_FS_A_N is the frame sync signal for DSPASP3FPGA and DSPASP0FPGA.
DSPASP0FPGA is an input data stream in SPORT format to SHARC1. Samples from the outputs of the
Format Decoder and from the various system inputs are multiplexed and mapped through the Input
Source Look-Up Table to this data signal.
DSPBSP3FPGA is the MAIN audio return signal from SHARC2 in SPORT format. The data present in
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this stream is converted to S/PDIF and I S formats and mapped via Look-Up Table to the output ports.
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SPORT_CLK_B is the serial shift clock for the data present on DSPBSP3FPGA.
SPORT_FS_B_N is the frame sync signal for DSPBSP3FPGA.
Video Interface
Signals: SYNC_DETECT, OSD_CS/, VIDEO_SCLK, VIDEO_DATA, VIDEO_REG, VID_I2C_DATA,
VID_I2C_SCLK
SYNC_DETECT is a signal that indicates the presence or absence of video synchronization from the
Video Board. This signal is stored in the Interrupt Status Register at bit 7. There is no interrupt assigned
to this signal, so the host processor simply polls this bit for its status.
OSD_CS/ is the chip select for the Fujitsu MB90092 OSD Controller device located on the Video Board.
This signal becomes active when transfers are initiated via the Video/OSD SPI interface. Transfer
initiation takes place when the two-byte commands for the MB90092 have been written to the OSD
Controller RAM. While the transfer is in progress, bit 6 is set in the Serial Interface Status Register.
VIDEO_SCLK, VIDEO_DATA, and VIDEO_REG comprise the remainder of the SPI interface to the On-
Screen Display controller and the video board control logic. Instructions are sent from either the OSD
control RAM or the Video control RAM inside the FPGA. The OSD control RAM is used to store the two-
byte commands that are sent to the OSD controller on the video board. The contents of the entire RAM
are shifted out of VIDEO_DATA synchronous with VIDEO_SCLK when a byte is written to the lower order
byte RAM. A status bit is set in the Serial Interface Status Register while the OSD RAM contents are
being shifted out. VIDEO_REG acts as a latch enable for the parallel register devices on the video board.
The Video Control RAM stores the instructions for the video logic. The entire contents of this RAM are
transmitted when a byte is written to address 6 within this RAM block.
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VID_I2C_SDATA and VID_I2C_SCLK comprise the I C control interface to the video CODEC. The host
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CPU writes data to storage registers within the FPGA, which in turn is transmitted to the CODEC using
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the I C protocol.
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