Lexicon RV-8 Service Manual page 130

RV-8 Service Manual
In overlay mode, composite or s-video luminance from the input amplifier is applied to YIN, and similarly,
s-video chrominance (if applicable) is applied to CIN. The video applied to YIN is shifted to have a back-
porch dc-level of about 1.57Vdc by U31 and associated circuitry. C123/C73 passively couple the ac-
content of the luminance signal, with the op-amp providing the dc response. The chroma channel is
biased to the same 1.57V level by R171/R172. The OSD video is related to program video by the
separate H and V syncs (GMHSYN/, VSYNC/) derived by the sync stripper (sheet 8).
The full-screen mode is independent of video and sync inputs. Raster generation is based on the
appropriate crystal clock.
The OSD luminance output is dc-shifted back to 0V back-porch level by U31 and associated circuitry.
C121/C122 passively couple the ac-content, with the op-amp providing the dc response. Chroma is
simply ac-coupled by C107/C108. The shifted OSD video is buffered and filtered by U30 to produce
OSD_SY_OUT and OSD_C_OUT. Switch U40 permits the S-video luminance to be turned off when
MSVID_YOFF is asserted high. OSD_Y+C_OUT is formed as half the sum of the buffer outputs. These
OSD output signals feed the output amplifiers as described earlier.
In order to produce usable overlays in the SECAM system, the OSD switching action is bypassed at high
frequency through U35 and R146, preserving an attenuated version of the fm color carriers.
On-Screen Display Serial Control (Video board schematic sheet 7)
The internal registers of the OSD are programmed serially from the main board in multiple 8-bit packets
on VIDEO_DATA, accompanied by VIDEO_SCLK, operating at 1 MHz. During routine OSD updating,
OSD_CS/ is level-shifted by U35, becoming OSD_CS5/, the OSD chip-select. The CPLD generates
OSD_SCLKG from the VIDEO_SCLK, and U35 drives OSD_SCLK5 to clock the data into the OSD chip.
Each logical transfer to the OSD chip consists of a pair of single-byte transfers.
Sync Stripper / DC Restorer (Video board schematic sheet 7)
Video from input amplifier U28 is fed through R204 to U41, which drives sync stripper U39 and the dc-
restorer formed by switch U40 and op amp U41.
Sync stripper U39 accepts analog video and extracts vertical and horizontal sync, producing logic level
VSYNC-OUT and AFC-OUT pulses respectively. A phase-locked loop based on ceramic resonator Y1
provides robust horizontal sync extraction even from noisy video sources. Pull-down resistors on the
outputs improve the pulse waveshapes. Sections of U42 buffer and shape the pulses from U39. AFC-
OUT is stretched by R244/C173 before buffering in order to meet the minimum width necessary for the
OSD chip.
Sections of U42 and the network formed by R243,R242,D11 and C172 form pulses that are aligned with
video back porch. These pulses switch U40, which in combination with integrator U41 forms a sample-
and-hold circuit that closes the feedback loop around the input video amplifier during back-porch time.
This acts to maintain the back-porch level at 0V. D10 limits the negative-going output of U41 in order to
minimize the undesirable effects of unusual sync patterns inherent in the macrovision video copy-
protection scheme.
Additional logic within U39 detects the presence of a valid video input. SYNC_DETECT is fed to the main
board for use in OSD management.
The sync stripper U39 is susceptible to small variations on its power supply, and so it is specially-powered
from a dedicated 5V regulator, U29.
With video input absent, AFC_OUT free-runs at around 15kHz.
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