Lexicon RV-8 Service Manual page 109

Lexicon
CRY_INTREQ/ is an interrupt line that indicates that DSPC has out-going control data and should be
serviced by the host CPU. When this interrupt occurs, bit 2 in the Interrupt Status Register is set. This bit
is then cleared after the host CPU polls this register. This interrupt is active low.
CRY_FINTREQ/ is an interrupt line that indicates that DSPAB has out-going control data and should be
serviced by the host CPU. When this interrupt occurs, bit 3 in the Interrupt Status Register is set. This bit
is then cleared after the host CPU polls this register. This interrupt is active low.
HINBSY is a status signal from the Format Decoder that indicates that control data written via the SPI
port has not yet been read by the decoder. This signal serves as a hold-off for the host CPU, preventing it
from over-writing control data before it has a chance to be implemented by the Format Decoder. The
state of this signal is stored within the Serial Interface Status Register at bit 7, which is continuously
polled by the host processor. When this bit is set high, the host will not write any further instructions via
the SPI port until the system software sees this bit UN-set to zero again.
DEC_IN_FSI is the word clock output to the Format Decoder that operates at 44.1kHz or 48kHz,
dependent upon the sampling rate of the source material multiplexed in on the DEC_SDI signal.
DEC_IN_SCKI is the sample clock 64FS output to the Format Decoder. DEC_SDI is synchronous with
this clock.
2
DEC_SDI is the I S formatted audio data input to the Format Decoder. Audio data from the system
P
P
S/PDIF inputs or from the signal MAIN_I2S_IN1 is multiplexed down to this one signal.
DEC_MCKI is the bit clock of the DEC_SDI stream and equivalent to 256FS.
DEC_OUT_SCKI is the sample clock 64FS output from the Format Decoder. Signals DEC_SDO[3:1] are
synchronous with this clock.
DEC_OUT_FSI is the word clock output from the Format Decoder that marks the sample frames on the
DEC_SDO outputs.
DEC_SDO[3:0] are the four data output streams from the Format Decoder. These streams carry the 5.1
decoded audio data. This data is further format for compliance to the Analog Devices SPORT
specification and routed to the SHARC devices.
SHARC Interface
Signals: DSPATXD, DSPARXD, DSPASPICLK, DSPASEL/, DSPBSEL/, DSPASP3FPGA,
DSPBSP3FPGA, DSPASP0FPGA, SPORT_CLKA_A, SPORT_FS_A_N, SPORT_CLK_B,
SPORT_FS_B_N
DSPATXD transmits control data to the SHARCs utilizing the Analog Devices SPI (Serial to Parallel
Interface) protocol. Control data is written to the internal SPI Control RAM by the system software and
serially shifted out via this pin. This signal is shared between both SHARC devices.
DSPARXD receives control status information from the SHARCs in serial form. This data is stored within
the SPI Control Status RAM and is polled by the system software. This signal is shared between both
SHARC devices.
DSPASPICLK is the shift clock used by the SPI protocol to serially shift data into and out of SHARCs.
DSPASEL/ is the chip select for the SPI port on SHARC1 (U18). This signal enables SPI communications
with U18. Setting bit 4 in the SPI Chip Select Register high enables it. Once this bit is set, then control
data is written to the SPI Control RAM, then the number of bytes to be shifted out on DSPATXD is written
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