Lexicon RV-8 Service Manual page 94

W4
W5
W6
W7
U18 JTAG ENABLED
General Purpose I/O
Device Pins: FLAG[9:4] (F3, E3, F2, F4, F1, G3)
Each flag pin may be configured as input or an output. In this application the flag pins listed above are
configured by software as outputs. An internal register controls each flag output. They are used as test
bits that activate status LEDs for each device. U15 provides increased drive capability for each flag pin to
light the LEDs, while resistor networks RP1 through RP3 provide a default pull down state for these pins
when the DSPs are being configured during the boot phase. When the devices are unconfigured, these
flag pins default to input mode.
Note that FLAG0 is no longer used in this application. Its function is non-descriptor.
Proprietary DSP A SDRAM and Flash (Sheet 4)
This sheet shows the interconnection between DSP A and its SDRAM. It also illustrates the boot
configuration for DSP A.
SDRAM (U6)
Each SHARC is supported by a 2 Mbit x 32 100MHz SDRAM. The memory interface is implemented as
four banks of 256-words. Each successive 256-word page is accessed by bank switching. The memory
device itself is non-linear as access is defined by row column address multiplexing. The SDRAM
addressing scheme is implemented via a 10-bit wide address bus. The mapping is defined as:
Column Address:A[7:0]
Row Address: A[10:0]
Each 256-word page is accessed across four banks, with each bank selected by two bits BA[1:0].
The SHARC devices contain a memory interface controller, which multiplexes an array of internal address
bits into the row-column scheme illustrated above. An integral part of the address muxing is the
6-18
U18
J17
TDI TDO
TCK
TMS
EMU/
TRST
Series Connection
Diagram
4
5
6
7
U37 JTAG ENABLED
RV-8 Service Manual
U37
TDI TDO
TCK
TMS
EMU/
TRST
U37 + U18 JTAG ENABLED
4
5
6
7