Lexicon RV-8 Service Manual page 97

Lexicon
Link Ports
Signals: DSPABLDATA[7:0], DSPBALDATA[7:0], L0CLK, L0ACK, L1CLK, L1ACK
The link port is a full duplex pathway that allows 100MHz bit rate transfers of audio data between the
SHARCs. The L0DAT[07:00] ports on each device are configured as transmitters while the
L1DAT[07:00] ports are configured as receivers. Data is transmitted from U16 to U34 on
DSPABLDATA[7:0] synchronous with the clock sourced from the L0CLK pin on U16. U34 receives this
data on the rising edge of this clock. When a transfer is complete, U34 transmits an acknowledge signal
to U16 via the L0ACK signal. Transfers in the opposite direction are handled the same way, except that
the clock source is on U34 while the acknowledge source is on U16.
Currently this application is not using the link ports, and as such this interconnection is only a provision for
future enhancements of capability.
SPORT Data Ports
Signals: SPORT_CLK_A, SPORT_FS_A_N, DSPASP3FPGA, DSPASP0FPGA, SPORT_CLK_B,
SPORT_FS_B_N, DSPBSP3FPGA
Each SHARC has four SPORT data ports comprised of a frame sync signal, a serial clock, and two bi-
directional data ports. U16 utilizes three of these ports. Port 0 is used as the receive data port, while Port
2 is used as a full duplex channel between U16 and U34. Port 3 is the return port for the Main Zone data.
Port 1 is unused. Timing is shared among all three used ports.
The SPORT data format is comprised of a serial bit stream of eight 32-bit samples, a serial shift clock and
a frame start signal. The audio data entering U16 on DSPASP0FPGA is comprised of samples from
2
either the system S/PDIF inputs, the outputs of the A/D Converters from the Analog IO Board, or the I S
P
P
streams output from the Format Decoder DSP. The selection of which stream is sent along to the SHARC
is done via data multiplexing within the AVRX FPGA. The data is clocked into the input buffers on the
SHARC by SPORT_CLK_A while the beginning of the data frame is marked by SPORT_FS_A_N.
SPORT data for the Main Zone is returned to the FPGA via DSPAP3FPGA. This data is synchronous
with SPORT_CLK_A with each frame start marked by SPORT_FS_A_N. This data is re-converted back
2
to the I S format via a look-up table operation within the AVRX FPGA.
P
P
DSPA2DSPB is a data path from U16 to U34 synchronous with SPORT_CLK_A and frame start marked
by SPORT_FS_A_N, while DSPB2DSPA is a data path from U34 to U16 synchronous with
SPORT_CLK_B and frame marked by SPORT_FS_B_N.
U34 provides a downmix data to the Analog IO Board via DSPBP3FPGA on SPORT port 3. This data is
2
converted back to I S data via look-up table operation within the FPGA. This data is synchronous with
P
P
SPORT_CLK_B and frame start marked by SPORT_FS_B_N. SPORT port 0 on U34 is a full duplex
communication channel to U16, and performs the same function as port 2 on U16.
The data ports are open drain, therefore need pull-up resistors R73, R74, and R140.
DSP/FPGA Power Conn. (Sheet 7)
This sheet shows the power and ground pin distribution within the SHARC devices and the regulator
scheme for the SHARC inner core power supply. This sheet also shows the glue logic CPLD and
interface to the VFD on the front panel.
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