Lexicon RV-8 Service Manual page 105

Lexicon
coming up. This is a likely scenario given the fact that the 3.3V rail is more heavily loaded than the 2.5V
rail.
There are seven ground pins associated with the core supply, and four associated with the I/O supply. In
addition, there are five no connect pins that are recommended by the manufacturer to be tied to GND. All
sixteen pins are tied to the DGND system plane.
Algorithm Storage FLASH RAM (U19)
The FLASH RAM is an ATMEL AT29LV040A 4Mbit device, organized as 512Kx8. 3.3 volts power this
device. It operates much like an EEPROM. Read cycles are identical to PROM operation with data output
on CRY_D[7:0] when chip select and output enable are both low. The output buffers enter a high
impedance state when either of these signals is high.
This device uses software data protection programming. Prior to writing data to this device, a series of
three programming commands must be presented at specific addresses. Data will not be written without
this sequence. The FLASH is organized as 2048 sectors of 256 bytes each. If any data within a sector is
to be changed, then the entire sector must be programmed. Each sector is erased automatically prior to
writing. Writing occurs when the WE/ and CE/ pins are low, and OE/ is high.
Main FPGA (Sheet 9)
This page contains the AVRX FPGA, which performs many salient functions to the main board. It is
packaged in a 208-pin QFP package. The AVRX FPGA converts and routes various digital audio formats
among the system I/O connectors and DSP processors, and has Serial Peripheral Interface (SPI) ports
that provide the means for the host processor to communicate to the system peripherals. It also has an
I2C interface for host communication to the video codec and it has interfaces for the IR remote control
and rotary encoder.
AVRX (U41)
Functionality is implemented within a Xilinx XC2S200 device. This device contains 200,000 logic gates,
75,264-bits of distributed RAM, and 56K bits of block RAM. 2.5V for core operation and 3.3V for IO
operation powers it. The FPGA may be configured either by the system software during the boot phase,
or by a 128K serial FLASH PROM during development.
Configuration
Resistors R157 and R158 select the programming mode of the FPGA. The default condition with R158
installed and R157 uninstalled configures the device as a slave operating in serial mode. In this operating
mode, the programming data is loaded into the device via the DIN_DATA0 pin (153) with the rising edge
of the signal appearing at the CCLK pin (155). The host processor provides both signals. In the
alternative scheme, R158 is uninstalled and R157 is installed. This places the FPGA in master serial
mode. This is appropriate for loading from a serial EPROM. In this mode of operation, the FPGA provides
a shift clock out of the CCLK pin to the programming EPROM, which in turn shifts programming data into
the DIN_DATA0 pin synchronous with this clock.
Resistors R128 through R131, R133 through R135, and R148 through R151 configure the source of
programming. The default condition routes the serial data and shift clock from the host CPU. In addition,
the INIT/, PROGRAM/, and DONE pins of the FPGA are routed to the host. The following table illustrates
the configuration for this mode.
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