Lexicon RV-8 Service Manual page 114

VCO Clock Control
Signals: MAIN_PLL_PUMP_UP, MAIN_PLL_PUMP_DN, MAIN_PLL_LOCK_DN/,
MAIN_PLL_FPGA_MCKO, ZONE2_PLL_PUMP_UP, ZONE2_PLL_PUMP_DN,
ZONE2_PLL_LOCK_DN/, REC_DAC_SEL[1:0], ZONE2_PLL_FPGA_MCKO, AUDIO_OSC
The AVRX FPGA uses the output frequency of each VCO implemented on RV-8 as a 512FS master clock
at 44.1/48kHz and a 256FS master clock at 88/96kHz. Within the AVRX, the incoming clock frequencies
are divided by 512 or 256 and is phase compared to a corresponding frequency derived from the
reference clock source. This clock reference is derived from the S/PDIF sample rate, or it can be derived
from the fixed crystal reference signal AUDIO_OSC. When the incoming master clock is too low
compared to the reference, a series of active high pulses are sent to the VCO forcing it to increase the
output frequency until a phase match occurs between the reference and the master clock. When the
incoming master clock frequency is too high compared to the reference, a series of active low pulses are
sent to the VCO forcing it to throttle back on the output frequency until phase match occurs. When the
two are matched, a series of low going pulses to the VCO that sustains oscillation at a stable point.
Further discussion as to the theory of VCO operation will be made later in this document.
MAIN_PLL_PUMP_UP is an active low signal that forces the master clock to increase in frequency when
the master clock rate is lower than the reference frequency.
MAIN_PLL_PUMP_DN/ is an active low signal that forces the master clock from the VCO to decrease in
frequency when the master clock rate is higher than the reference frequency.
MAIN_PLL_LOCK_DN/ is an active low signal that keeps the master clock from the VCO at a stable rate
of oscillation when the master clock is equal to the reference frequency.
MAIN_PLL_FPGA_MCKO is the master clock output from the VCO for the Main Zone.
A set of analogous signals exists for the Zone 2 PLL circuitry. Their function is exactly the same as their
Main Zone counterparts, so further discussion would be redundant. The signals in question are:
ZONE2_PLL_PUMP_UP, ZONE2_PLL_PUMP_DN/, ZONE2_PLL_LOCK_DN/, and
ZONE2_PLL_FPGA_MCKO.
The Zone 2 D/A and A/D converter master clocks may be sourced from either the Main or Zone 2 VCOs.
Two control register bits within the Clock Source Select #2 register make the source selection. The
following table further illustrates the selection conditions.
Master Clock Source Select Table
Master Clock Source Select
05 03 REC_ADC_MCKI/
0 0 ZONE 2 PLL
0 1 ZONE 2 PLL
1 0 MAIN ZONE PLL
1 1 MAIN ZONE PLL (Default)
6-38
REC_DAC_MCKI/
ZONE 2 PLL
MAIN ZONE PLL
ZONE 2 PLL
MAIN ZONE PLL (Default)
RV-8 Service Manual