Lexicon RV-8 Service Manual page 202

8 7
+5VD
R131 R129
D
4.7K 4.7K
R128
FPGA_INIT/
[1/B8]
XFLASH_INIT/
[10/D8]
R130
FPGA_PROG/
[1/B8]
R135
XFLASH_CF/ *
[10/C3]
CPUADDR[20:0]
[1/D3,7/B5]
CPUCS2/
[1/B3,2/C7]
CPUWRL/
[1/B3,7/B5]
CPURD/
[1/B3,7/B5]
CPUCLKOUT
[1/D8]
FPGA_RESET/
[2/B4]
WRDCLKMON
[2/D3]
IR_IN2
[18/C3]
MAIN_I2S_IN[3:1]
[12/C3]
C
SPDIF_COAX_IN[4:1]
[13/D5]
SPDIF_OPTO_IN[4:1]
[13/B5]
DSPASP3FPGA
[6/D6]
DSPASP0FPGA
[6/C7]
SPORT_CLK_A
[6/D7]
SPORT_FS_A_N
[6/D7]
SPORT_CLK_B
[6/C7]
DSPBSP3FPGA
[6/B7]
SPORT_FS_B_N
[6/C7]
DEC_SDO0
[8/B3]
DEC_SDO1
[8/B3]
DEC_SDO2
[8/B3]
DEC_SDO3
[8/B3]
DEC_SDI
[8/B7]
DEC_IN_FSI
[8/B8]
DEC_IN_SCKI
[8/B8]
B
EXP[17:0]
[11/B7]
HINBSY
[8/C8]
ADA_TUN_CE/
[12/D4]
ZONE2_PLL_MCKO
[16/B2]
MAIN_PLL_MCKO
[15/B2]
AUDIO_OSC
[10/B3]
A
1 FPGA_TDI
2 FPGA_TDO
3 FPGA_TMS
4 FPGA_TCK
J19
*
8 7
6
+3.3VD
+3.3VD
VCCO 3.3V
R158
52
M0
R134 R133 50
R157 M1
4.7K 4.7K 54
M2
* *
*
107
INIT
106
PROGRAM
CPUADDR9 96
HOST_ADR09
CPUADDR8 75
HOST_ADR08
CPUADDR7 74
HOST_ADR07
CPUADDR6 73
HOST_ADR06
CPUADDR5 71
HOST_ADR05
CPUADDR4 70
HOST_ADR04
CPUADDR3 69
HOST_ADR03
CPUADDR2 68
HOST_ADR02
CPUADDR1 67
HOST_ADR01
CPUADDR0 63
HOST_ADR00
84
CS_N
83
WR_N
95
RD_N
77
HOST_CLK_PIN
148
RESET_N
154
WORDCLK_SH7014
90
IR_IN2
MAIN_I2S_IN3 15
MAIN_I2S_IN3
MAIN_I2S_IN2 10
MAIN_I2S_IN2
MAIN_I2S_IN1 14
MAIN_I2S_IN1
SPDIF_COAX_IN1 166
SPDIF_COAX_IN1
SPDIF_COAX_IN4 165
SPDIF_COAX_IN4
SPDIF_COAX_IN2 164
SPDIF_COAX_IN2
SPDIF_COAX_IN3 167
SPDIF_COAX_IN3
SPDIF_OPTO_IN1 163
SPDIF_OPTO_IN1
SPDIF_OPTO_IN2 162
SPDIF_OPTO_IN2
SPDIF_OPTO_IN3 161
SPDIF_OPTO_IN3
SPDIF_OPTO_IN4 160
SPDIF_OPTO_IN4
89
SHRC1_SPORT_IN1
88
SHRC1_SPORT_OUT1
RP17 7 2 47 100
SPORT_CLK
RP18 6 3 47 87
SPORT_FRAME
RP17 6 3 47
86
SHRC2_SPORT_IN1
RP18 7 2 47
122
DEC_I2S_IN1
123
DEC_I2S_IN2
125
DEC_I2S_IN3
127
DEC_I2S_IN4
136
DEC_I2S_OUT1
RP14 7 2 47 140
DEC_FRAME
RP14 8 1 47 141
DEC_CLK
EXP0 187
EXP0
EXP1 188
EXP1
EXP2 189
EXP2
EXP3 191
EXP3
EXP4 192
EXP4
EXP5 193
EXP5
EXP6 194
EXP6
EXP7 195
EXP7
EXP8 199
EXP8
EXP9 200
EXP9
EXP10 201
EXP10
EXP11 202
EXP11
EXP12 203
EXP12
EXP13 204
EXP13
EXP14 205
EXP14
EXP15 206
EXP15
EXP16 149
EXP16
EXP17 150
EXP17
152
HINBSY
27
TUNER_CE_N
80
ZONE2_PLL_CLK
185
MAIN_PLL_CLK
182
OSC_14_112MHZ_PIN
+3.3VD
159
TDI
157
TDO
2
TMS
207
TCK
R154 R155 R156
4.7K 4.7K 4.7K
6
5 4
+3.3VD
+2.5VD
VCCINT 2.5V
155
CCLK
104
DONE
153
XC2S200
DIN_DATA0
147
BUF_DIR
108 LVDATA7
HOST_DATA7
115 LVDATA6
HOST_DATA6
119 LVDATA5
HOST_DATA5
126 LVDATA4
HOST_DATA4
135 LVDATA3
HOST_DATA3
142 LVDATA2
HOST_DATA2
146 LVDATA1
HOST_DATA1
82 LVDATA0
HOST_DATA0
113
IRQ0_N
112
IRQ1
111
IRQ2_N
110
IRQ3_N
109
IRQ7_N
62
IR1_IN
59 RP28 1
FP_SER_IN
58 RP28 2
FP_SER_OUT
57 RP28 3
FP_SER_CLK
49 RP28 4
FP_SER_LTCH
61
ENC_IN1
60
ENC_IN2
94
SPI1_IN
129 RP15 4
SPI1_OUT
132 RP15 3
SPI1_CLK
133 RP15 2
SPI1_DS_N
97
DSPC_SEL
98
RDSDAT
99
RDSCLK
151 R152
SPI2_DS_N
114
CRY_IN
134 RP15 1
CRY_OUT
138 RP14 4
CRY_CLK
139 RP14 3
CRY_FCS_N
120
CRY_SCS_N
102
CRY_INTREQ_N
121
CRY_FINTREQ_N
81
WCLKDIV8INT_N
35 RP25 3
VIDSTAT
37 RP25 1
VID_CS_N
41 RP26 4
VID_SCLK
42 RP26 3
VID_DATA
36 RP25 2
VID_LTCH
43
VID_I2C_DATA
44
VID_I2C_CLK
30 RP24 7
ADA_SDATA_IN
29 RP24 8
ADA_SDATA_OUT
31 RP24 6
ADA_SCLK
34 RP25 4
ADA_LATCH
33
ADA_VC_SEL_N
101 RP17 1
SPDIF_OUT
6 RP20 8
MAIN_I2S1_OUT
8 RP20 6
MAIN_I2S2_OUT
7 RP20 7
MAIN_I2S3_OUT
9 RP20 5
MAIN_I2S4_OUT
18 RP21 5
REC_DAC_I2S_OUT
20 RP22 8
MAIN_I2S_IN4
23 RP23 8
MAIN_FS_N
16 RP21 8
MAIN_FS64_N
3 RP19 8
DEC_MCKI
22 RP22 6
REC_ADC_FS_N
17 RP21 6
REC_ADC_FS64_N
4 RP19 6
REC_DAC_SEL1
24 RP23 6
REC_DAC_FS_N
21 RP22 7
REC_DAC_FS64_N
5 RP19 5
REC_DAC_SEL0
180 RP16 6
AMP1_SER_IN
179 RP16 7
AMP1_SER_OUT
181 RP16 5
AMP1_SER_CLK
178 RP16 8
AMP1_SER_LTCH
48
AMP2_SER_IN
46 RP27 3
AMP2_SER_OUT
47 RP27 2
AMP2_SER_CLK
45 RP27 4
AMP2_SER_LTCH
168
MAIN_PLL_UP
173
MAIN_PLL_DOWN_SLOW
172
MAIN_PLL_DOWN_FAST
174
ZONE2_PLL_UP
176
ZONE2_PLL_DOWN_SLOW
175
ZONE2_PLL2_DOWN_FAST
RP23 7
RP21 7
GND
RP19 7
U41
NC
NC
5 4
3
R148 FPGA_CCLK
[1/A6]
R149 XFLASH_CCLK
*
[10/D8]
FPGA_DONE
[1/B8,10/D8]
R151 XFLASH_DIN
*
[10/D3]
R150 FPGA_SDATA
[1/B7]
BUFDIR
[2/C4]
LVDATA[15:0]
[2/D4]
LVKYBDIRQ/
[2/D3]
DISP_CTRL
[7/B5]
LVDSPABIRQ/
[2/D3]
LVCRYIRQ/
[2/D3]
LVVIDTUNIRQ/
[2/D3]
FP_IR_IN1
[12/B6]
8 47 FP_SDATA_IN
[12/B6]
7 47 FP_SDATA_OUT
[12/B6]
6 47 FP_SDATA_CLK
[12/B6]
5 47 FP_SDATA_LTCH
[12/B6]
FP_ENCA_IN
[12/B6]
FP_ENCB_IN
[12/B6]
DSPATXD
[6/D6,8/C8]
5 47 DSPARXD
[6/D6,8/C8]
6 47 DSPASPICLK
[6/D6,8/C8]
7 47 DSPASEL/
[6/D7]
CRY_CLKSEL
[8/A8]
TUN_RDS_DAT
[12/D3]
TUN_RDS_CLK
[12/D3]
47 DSPBSEL/
[6/C7]
CRY_TXD
[8/D8]
8 47 CRY_RXD
[8/D8]
5 47 CRY_SPICLK
[8/D8]
6 47 CRY_FCS/
[8/C7]
CRY_SCS/
[8/D7]
CRY_INTREQ/
[8/D7]
CRY_FINTREQ/
[8/C7]
WCLKDIV8INT/
[3/C8]
6 47 SYNC_DETECT
[12/B4]
8 47 OSD_CS/
[12/B4]
5 47 VIDEO_SCLK
[12/B4]
6 47 VIDEO_DATA
[12/B4]
7 47 VIDEO_REG
[12/B4]
VID_I2C_SDATA
[12/B3]
VID_I2C_SCLK
[12/B4]
2 47 ADA_SDATA_IN
[12/D3]
1 47 ADA_SDATA_OUT
[12/D4]
3 47 ADA_SCLK
[12/D4]
5 47 ADA_LATCH
[12/D4]
ADA_VC_SEL/
[12/D4]
8 47 DIG_REC_OUT
[13/B8]
1 47 MAIN_I2S_OUT1
3 47 MAIN_I2S_OUT2
2 47 MAIN_I2S_OUT3
MAIN_I2S_OUT[4:1]
4 47 MAIN_I2S_OUT4
[12/C4]
4 47 REC_DAC_I2S_OUT
[12/C4]
1 47 MAIN_I2S_IN4
[12/D4]
1 47 MAIN_FS/
[12/D4]
1 47 MAIN_FS64/
[12/C4]
1 47 MAIN_FS256/
[12/C4]
3 47 REC_ADC_FS/
[12/D4]
3 47 REC_ADC_FS64/
[12/C4]
3 47 REC_ADC_MCKI/
[12/C4]
3 47 REC_DAC_FS/
[12/D4]
2 47 REC_DAC_FS64/
[12/D4]
4 47 REC_DAC_MCKI/
[12/C4]
3 47 CTRL_DATA
[12/B8]
2 47 STAT_DATA
[12/B7]
4 47 SER_CLKA
[12/B8]
1 47 DATA_LATCHA
[12/B8]
CTRL_DATB
[12/B8]
6 47 STAT_DATB
[12/B7]
7 47 SER_CLKB
[12/B8]
5 47 DATA_LATCHB
[12/B8]
MAIN_PLL_PUMP_UP
[15/C8]
MAIN_PLL_LOCK_DN/
[15/B8]
MAIN_PLL_PUMP_DN/
[15/B8]
ZONE2_PLL_PUMP_UP
[16/C8]
ZONE2_PLL_LOCK_DN/
[16/B8]
ZONE2_PLL_PUMP_DN/
[16/B8]
2 47 DEC_OUT_FSI
[8/B3]
2 47 DEC_OUT_SCKI
[8/B3]
2 47 DEC_MCKI
[8/B3]
3
2 1
REVISIONS
DRAFTER Q.C.
REV DESCRIPTION
CHECKER AUTH.
RWH CW
1 CHANGED PER DCR 020913-00
11/05/02 12/20/02
CAM MAG
11/06/02 12/20/02
RWH CW
2 CHANGED PER DCR 030307-00
5/2/03 5/20/03
CAM MAG
5/14/03 5/20/03
RWH ECM D
3 CHANGED PER DCR 030626-00
9/29/03 10/9/03
CAM MAG
10/2/03 10/9/03
C
B
SPARES
NC RP17 4 5 47 NC
NC RP18 5 4 47 NC
NC RP18 8 1 47 NC
NC RP22 5 4 47 NC
NC RP23 5 4 47 NC
NC RP24 5 4 47 NC
NC RP26 7 2 47 NC
NC RP26 8 1 47 NC
NC RP27 8 1 47 NC
A
CONTRACT
exicon
3 OAK PARK
NO.
BEDFORD, MA 01730
TITLE
APPROVALS DATE
SCHEM, MAIN BD,RV8
DRAWN
RWH 4/26/02
MAIN FPGA
CHECKED
SIZE CODE NUMBER REV
CAM 4/30/02
B
3
060-15559
Q.C.
CW 5/1/02
FILE NAME
ISSUED
JV 4/30/02 15559-6 . 9 SHEET 9 OF 19
2 1