Lexicon RV-8 Service Manual page 131

Lexicon
Video Control Registers (Video board schematic sheet 8).
Control registers are implemented within CPLD U14, through a serial interface. The serial clock and data
are VIDEO_SCLK and VIDEO_DATA, shared in common with the OSD. A transfer is initiated by a pulse
on VIDEO_REG/, followed by a burst of clock and data that update all 56 control register bits within the
CPLD in approximately 4.5 sec. All control bits are initialized to 0 at power-up by VIDEO_RST/.
Logic within the CPLD derives additional control bits from the values in the registers. For example, the
MSVID_SELn bits are formed by gating the MVID_SELn bits with MCVID_EN/ such that the
MSVID_SELn bits are forced to 0 when MCVID_EN/ is low.
The CPLD can be programmed in-circuit through the JTAG port J17.
Font Flash Programming Interface (Video board schematic sheet 9).
The CPLD U14 also controls the in-system programming of flash memory U25, which holds the
bitmapped OSD font pattern. The CPLD is interfaced to the memory D[7:0] and A[15:0] buses.
In normal operation, this interface is tri-stated outputs and does not drive the buses, and the only bus
activity is the fetching of font patterns from U25 over the A[15:0], D[7:0] buses under the control of OSD
U26.
When necessary, the host processor on the main board manages the programming of the font flash
memory. A large white box on the OSD is a symptom of an un-programmed memory. A control-register
transfer with bit 47 set initiates a font flash write cycle, based on a state machine in the CPLD. The CPLD
address and data buses are enabled, the OSD releases control of the bus (OSD_TSC/=high), and
VROM_WR/ is asserted to write to the flash memory. The host performs a series of transfers with
updated address and data to program subsequent bytes into the flash. During programming, the OSD
continues to operate, but the write operations interfere with the normal bitmap fetching, which temporarily
corrupts the OSD image. When the writing is complete, the corruption ceases, and the image is stable.
Power and Control Interface (Video board schematic sheet 10).
J20 is the control and status interface to the host. J18 supplies power from a connector on the main
board. The main video +5-volt rail is +5VV, a filtered version of system +5VD, which also supplies relay
coils through FB4. The negative rail is -5VV, derived from the main board -15VA by regulator U32. The
video codec U34 and CPLD U14 are powered by 3.3V from regulator U24.
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